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Support incremental builds for the bitstream.

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By patching the UDS and UDI into an already built bitstream, it is now
not necessary to rebuild the entire build flow when changing the UDS
and the UDI. This lowers re-build times significantly.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-11-28 10:20:30 +01:00 • committed by Michael Cardell Widerkrantz
parent 29fd8338a7
commit 8731908cb1
No known key found for this signature in database
GPG key ID: D3DB3DDF57E704E5
6 changed files with 165 additions and 15 deletions
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17
hw/application_fpga/core/uds/rtl/uds.v
View file

@ -36,9 +36,6 @@ module uds(
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] uds_reg [0 : 7];
initial $readmemh(`UDS_HEX, uds_reg);
reg uds_rd_reg [0 : 7];
reg uds_rd_we;
@ -57,6 +54,17 @@ module uds(
assign ready = tmp_ready;
//----------------------------------------------------------------
// uds rom instance.
//----------------------------------------------------------------
uds_rom rom_i(
.addr(address),
.re(uds_rd_we),
.data(tmp_read_data)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
@ -85,7 +93,6 @@ module uds(
always @*
begin : api
uds_rd_we = 1'h0;
tmp_read_data = 32'h0;
tmp_ready = 1'h0;
if (cs) begin
@ -94,14 +101,12 @@ module uds(
if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
if (!fw_app_mode) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
tmp_read_data = uds_reg[address[2 : 0]];
uds_rd_we = 1'h1;
end
end
end
end
end
endmodule // uds
//======================================================================

39
hw/application_fpga/core/uds/rtl/uds_rom.v Normal file
View file

@ -0,0 +1,39 @@
//======================================================================
//
// uds_rom.v
// ---------
// UDS rom. Generated by instantiating named SB_LUT4 resources.
// Note: This makes the design technology specific.
//
//
// Author: Claire Xenia Wolf
// Copyright (C) 2023 - YosysHQ, Tillitis AB
// SPDX-License-Identifier: GPL-2.0-only
//
//======================================================================
`default_nettype none
module uds_rom(
input wire [2:0] addr,
input wire re,
output wire [31:0] data
);
generate
genvar ii;
for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts
(* uds_rom_idx=ii, keep *) SB_LUT4
#(
.LUT_INIT({8'ha6 ^ ii[7:0], 8'h00})
) lut_i (
.I0(addr[0]), .I1(addr[1]), .I2(addr[2]), .I3(re),
.O(data[ii])
);
end
endgenerate
endmodule // uds_rom
//======================================================================
// EOF uds_rom.v
//======================================================================