Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity

Add CPU execution monitor

Browse Source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-02-20 14:52:25 +01:00 committed by Daniel Lublin
parent e514f778b2
commit 86ea45e10a
No known key found for this signature in database
GPG Key ID: 75BD0FEB8D3E7830
3 changed files with 153 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

143
hw/application_fpga/core/tk1/rtl/tk1.v
View File

@ -20,6 +20,12 @@ module tk1(
input wire cpu_trap, input wire cpu_trap,
output wire fw_app_mode, output wire fw_app_mode,
input wire [31 : 0] cpu_addr,
input wire cpu_instr,
input wire cpu_valid,
output wire force_jump,
output wire [31 : 0] jump_instr,
output wire led_r, output wire led_r,
output wire led_g, output wire led_g,
output wire led_b, output wire led_b,
@ -70,6 +76,11 @@ module tk1(
localparam ADDR_UDI_FIRST = 8'h30; localparam ADDR_UDI_FIRST = 8'h30;
localparam ADDR_UDI_LAST = 8'h31; localparam ADDR_UDI_LAST = 8'h31;
localparam ADDR_CPU_MON_CTRL = 8'h60;
localparam ADDR_CPU_MON_FIRST = 8'h61;
localparam ADDR_CPU_MON_LAST = 8'h62;
localparam ADDR_CPU_MON_INSTR = 8'h63;
localparam TK1_NAME0 = 32'h746B3120; // "tk1 " localparam TK1_NAME0 = 32'h746B3120; // "tk1 "
localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf" localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf"
localparam TK1_VERSION = 32'h00000004; localparam TK1_VERSION = 32'h00000004;
@ -112,6 +123,15 @@ module tk1(
reg [2 : 0] cpu_trap_led_new; reg [2 : 0] cpu_trap_led_new;
reg cpu_trap_led_we; reg cpu_trap_led_we;
reg cpu_mon_en_reg;
reg cpu_mon_en_we;
reg [31 : 0] cpu_mon_first_reg;
reg cpu_mon_first_we;
reg [31 : 0] cpu_mon_last_reg;
reg cpu_mon_last_we;
reg [31 : 0] cpu_mon_instr_reg;
reg cpu_mon_instr_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
@ -119,6 +139,7 @@ module tk1(
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
reg [31 : 0] tmp_read_data; reg [31 : 0] tmp_read_data;
reg tmp_ready; reg tmp_ready;
reg tmp_force_jump;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg [2 : 0] muxed_led; reg [2 : 0] muxed_led;
@ -132,6 +153,9 @@ module tk1(
assign fw_app_mode = switch_app_reg; assign fw_app_mode = switch_app_reg;
assign force_jump = tmp_force_jump;
assign jump_instr = cpu_mon_instr_reg;
assign gpio3 = gpio3_reg; assign gpio3 = gpio3_reg;
assign gpio4 = gpio4_reg; assign gpio4 = gpio4_reg;
@ -164,25 +188,29 @@ module tk1(
always @ (posedge clk) always @ (posedge clk)
begin : reg_update begin : reg_update
if (!reset_n) begin if (!reset_n) begin
switch_app_reg <= 1'h0; switch_app_reg <= 1'h0;
led_reg <= 3'h0; led_reg <= 3'h6;
gpio1_reg <= 2'h0; gpio1_reg <= 2'h0;
gpio2_reg <= 2'h0; gpio2_reg <= 2'h0;
gpio3_reg <= 1'h0; gpio3_reg <= 1'h0;
gpio4_reg <= 1'h0; gpio4_reg <= 1'h0;
app_start_reg <= 32'h0; app_start_reg <= 32'h0;
app_size_reg <= 32'h0; app_size_reg <= 32'h0;
blake2s_addr_reg <= 32'h0; blake2s_addr_reg <= 32'h0;
cdi_mem[0] <= 32'h0; cdi_mem[0] <= 32'h0;
cdi_mem[1] <= 32'h0; cdi_mem[1] <= 32'h0;
cdi_mem[2] <= 32'h0; cdi_mem[2] <= 32'h0;
cdi_mem[3] <= 32'h0; cdi_mem[3] <= 32'h0;
cdi_mem[4] <= 32'h0; cdi_mem[4] <= 32'h0;
cdi_mem[5] <= 32'h0; cdi_mem[5] <= 32'h0;
cdi_mem[6] <= 32'h0; cdi_mem[6] <= 32'h0;
cdi_mem[7] <= 32'h0; cdi_mem[7] <= 32'h0;
cpu_trap_ctr_reg <= 24'h0; cpu_trap_ctr_reg <= 24'h0;
cpu_trap_led_reg <= 3'h0; cpu_trap_led_reg <= 3'h0;
cpu_mon_en_reg <= 1'h0;
cpu_mon_first_reg <= 32'h0;
cpu_mon_last_reg <= 32'h0;
cpu_mon_instr_reg <= 32'h0;
end end
else begin else begin
@ -229,6 +257,22 @@ module tk1(
if (cpu_trap_led_we) begin if (cpu_trap_led_we) begin
cpu_trap_led_reg <= cpu_trap_led_new; cpu_trap_led_reg <= cpu_trap_led_new;
end end
if (cpu_mon_en_we) begin
cpu_mon_en_reg <= write_data[0];
end
if (cpu_mon_first_we) begin
cpu_mon_first_reg <= write_data;
end
if (cpu_mon_last_we) begin
cpu_mon_last_reg <= write_data;
end
if (cpu_mon_instr_we) begin
cpu_mon_instr_reg <= write_data;
end
end end
end // reg_update end // reg_update
@ -256,22 +300,45 @@ module tk1(
end end
//----------------------------------------------------------------
// cpu_monitor
//----------------------------------------------------------------
always @*
begin : cpu_monitor
tmp_force_jump = 1'h0;
if (cpu_mon_en_reg) begin
if (cpu_valid && cpu_instr) begin
if ((cpu_addr >= cpu_mon_first_reg) &&
(cpu_addr <= cpu_mon_last_reg)) begin
tmp_force_jump = 1'h1;
end
end
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// api // api
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @*
begin : api begin : api
switch_app_we = 1'h0; switch_app_we = 1'h0;
led_we = 1'h0; led_we = 1'h0;
gpio3_we = 1'h0; gpio3_we = 1'h0;
gpio4_we = 1'h0; gpio4_we = 1'h0;
app_start_we = 1'h0; app_start_we = 1'h0;
app_size_we = 1'h0; app_size_we = 1'h0;
blake2s_addr_we = 1'h0; blake2s_addr_we = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
tmp_read_data = 32'h0; cpu_mon_en_we = 1'h0;
tmp_ready = 1'h0; cpu_mon_first_we = 1'h0;
cpu_mon_last_we = 1'h0;
cpu_mon_instr_we = 1'h0;
cpu_mon_en_we = 1'h0;
tmp_read_data = 32'h0;
tmp_ready = 1'h0;
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
@ -312,6 +379,22 @@ module tk1(
cdi_mem_we = 1'h1; cdi_mem_we = 1'h1;
end end
end end
if (address == ADDR_CPU_MON_CTRL) begin
cpu_mon_en_we = 1'h1;
end
if (address == ADDR_CPU_MON_FIRST) begin
cpu_mon_first_we = 1'h1;
end
if (address == ADDR_CPU_MON_LAST) begin
cpu_mon_last_we = 1'h1;
end
if (address == ADDR_CPU_MON_INSTR) begin
cpu_mon_instr_we = 1'h1;
end
end end
else begin else begin

50
hw/application_fpga/rtl/application_fpga.v
View File

@ -70,6 +70,7 @@ module application_fpga(
wire cpu_trap; wire cpu_trap;
wire cpu_valid; wire cpu_valid;
wire cpu_instr;
wire [03 : 0] cpu_wstrb; wire [03 : 0] cpu_wstrb;
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
wire [31 : 0] cpu_addr; wire [31 : 0] cpu_addr;
@ -150,6 +151,8 @@ module application_fpga(
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire fw_app_mode; wire fw_app_mode;
wire force_jump;
wire [31 : 0] jump_instr;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -185,7 +188,7 @@ module application_fpga(
.eoi(), .eoi(),
.trace_valid(), .trace_valid(),
.trace_data(), .trace_data(),
.mem_instr(), .mem_instr(cpu_instr),
.mem_la_read(), .mem_la_read(),
.mem_la_write(), .mem_la_write(),
.mem_la_addr(), .mem_la_addr(),
@ -204,6 +207,9 @@ module application_fpga(
rom rom_inst( rom rom_inst(
.force_jump(force_jump),
.jump_instr(jump_instr),
.cs(rom_cs), .cs(rom_cs),
.address(rom_address), .address(rom_address),
.read_data(rom_read_data), .read_data(rom_read_data),
@ -308,28 +314,34 @@ module application_fpga(
tk1 tk1_inst( tk1 tk1_inst(
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cpu_trap(cpu_trap), .cpu_trap(cpu_trap),
.fw_app_mode(fw_app_mode), .fw_app_mode(fw_app_mode),
.led_r(led_r), .cpu_addr(cpu_addr),
.led_g(led_g), .cpu_instr(cpu_instr),
.led_b(led_b), .cpu_valid(cpu_valid),
.force_jump(force_jump),
.jump_instr(jump_instr),
.gpio1(app_gpio1), .led_r(led_r),
.gpio2(app_gpio2), .led_g(led_g),
.gpio3(app_gpio3), .led_b(led_b),
.gpio4(app_gpio4),
.cs(tk1_cs), .gpio1(app_gpio1),
.we(tk1_we), .gpio2(app_gpio2),
.address(tk1_address), .gpio3(app_gpio3),
.write_data(tk1_write_data), .gpio4(app_gpio4),
.read_data(tk1_read_data),
.ready(tk1_ready) .cs(tk1_cs),
); .we(tk1_we),
.address(tk1_address),
.write_data(tk1_write_data),
.read_data(tk1_read_data),
.ready(tk1_ready)
);
//---------------------------------------------------------------- //----------------------------------------------------------------

10
hw/application_fpga/rtl/rom.v
View File

@ -15,6 +15,9 @@
`default_nettype none `default_nettype none
module rom( module rom(
input wire force_jump,
input wire [31 : 0] jump_instr,
input wire cs, input wire cs,
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
input wire [11 : 0] address, input wire [11 : 0] address,
@ -60,7 +63,12 @@ module rom(
begin : rom_logic begin : rom_logic
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
rom_rdata = memory[address]; if (force_jump) begin
rom_rdata = jump_instr;
end
else begin
rom_rdata = memory[address];
end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
rom_ready = cs; rom_ready = cs;
end end