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Add CPU execution monitor

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-02-20 14:52:25 +01:00 • committed by Daniel Lublin
parent e514f778b2
commit 86ea45e10a
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GPG key ID: 75BD0FEB8D3E7830
3 changed files with 153 additions and 50 deletions
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50
hw/application_fpga/rtl/application_fpga.v
View file

@ -70,6 +70,7 @@ module application_fpga(
wire cpu_trap;
wire cpu_valid;
wire cpu_instr;
wire [03 : 0] cpu_wstrb;
/* verilator lint_off UNUSED */
wire [31 : 0] cpu_addr;
@ -150,6 +151,8 @@ module application_fpga(
wire [31 : 0] tk1_read_data;
wire tk1_ready;
wire fw_app_mode;
wire force_jump;
wire [31 : 0] jump_instr;
//----------------------------------------------------------------
@ -185,7 +188,7 @@ module application_fpga(
.eoi(),
.trace_valid(),
.trace_data(),
.mem_instr(),
.mem_instr(cpu_instr),
.mem_la_read(),
.mem_la_write(),
.mem_la_addr(),
@ -204,6 +207,9 @@ module application_fpga(
rom rom_inst(
.force_jump(force_jump),
.jump_instr(jump_instr),
.cs(rom_cs),
.address(rom_address),
.read_data(rom_read_data),
@ -308,28 +314,34 @@ module application_fpga(
tk1 tk1_inst(
.clk(clk),
.reset_n(reset_n),
.clk(clk),
.reset_n(reset_n),
.cpu_trap(cpu_trap),
.fw_app_mode(fw_app_mode),
.cpu_trap(cpu_trap),
.fw_app_mode(fw_app_mode),
.led_r(led_r),
.led_g(led_g),
.led_b(led_b),
.cpu_addr(cpu_addr),
.cpu_instr(cpu_instr),
.cpu_valid(cpu_valid),
.force_jump(force_jump),
.jump_instr(jump_instr),
.gpio1(app_gpio1),
.gpio2(app_gpio2),
.gpio3(app_gpio3),
.gpio4(app_gpio4),
.led_r(led_r),
.led_g(led_g),
.led_b(led_b),
.cs(tk1_cs),
.we(tk1_we),
.address(tk1_address),
.write_data(tk1_write_data),
.read_data(tk1_read_data),
.ready(tk1_ready)
);
.gpio1(app_gpio1),
.gpio2(app_gpio2),
.gpio3(app_gpio3),
.gpio4(app_gpio4),
.cs(tk1_cs),
.we(tk1_we),
.address(tk1_address),
.write_data(tk1_write_data),
.read_data(tk1_read_data),
.ready(tk1_ready)
);
//----------------------------------------------------------------

10
hw/application_fpga/rtl/rom.v
View file

@ -15,6 +15,9 @@
`default_nettype none
module rom(
input wire force_jump,
input wire [31 : 0] jump_instr,
input wire cs,
/* verilator lint_off UNUSED */
input wire [11 : 0] address,
@ -60,7 +63,12 @@ module rom(
begin : rom_logic
/* verilator lint_off WIDTH */
rom_rdata = memory[address];
if (force_jump) begin
rom_rdata = jump_instr;
end
else begin
rom_rdata = memory[address];
end
/* verilator lint_on WIDTH */
rom_ready = cs;
end