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PoC: Make sensitive assets only readable/writable before system_mode is set

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After the first time system_mode is set to one, the assets will no
longer be read- or writeable, even if system_mode is set to zero at a
later syscall. This is to make sure syscalls does not have the same
privilege as the firmware has at first boot.

We need to monitor when system_mode is set to one, otherwise we might
accedentially lock the assets before actually leaving firmware, for
example if firmware would use a function set in any of the registers
used in system_mode_ctrl.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>
This commit is contained in:
Daniel Jobson 2024-11-15 11:19:40 +01:00 • committed by Mikael Ågren
parent eacfd6eddc
commit 833bf63bc8
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GPG key ID: E02DA3D397792C46
5 changed files with 44 additions and 24 deletions
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6
hw/application_fpga/tb/application_fpga_sim.v
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@ -166,7 +166,7 @@ module application_fpga_sim (
reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data;
wire tk1_ready;
wire system_mode;
wire rw_locked;
wire force_trap;
wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand;
@ -305,7 +305,7 @@ module application_fpga_sim (
.clk(clk),
.reset_n(reset_n),
.system_mode(system_mode),
.en(~rw_locked),
.cs(uds_cs),
.address(uds_address),
@ -353,7 +353,7 @@ module application_fpga_sim (
.clk(clk),
.reset_n(reset_n),
.system_mode(system_mode),
.rw_locked(rw_locked),
.cpu_addr (cpu_addr),
.cpu_instr (cpu_instr),