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https://github.com/tillitis/tillitis-key1.git
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FPGA: Add CPU instruction address SPI access control
Add logic that checks if the CPU is reading an instruction to execute from ROM or not. If instructions are read from ROM, access to the SPI from the API is granted, and signals between the SPI master and a slave are allowed. If instructions are not read from ROM, any API access is blocked. and between the SPI master and a slave are disabled. Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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@ -106,6 +106,8 @@ module tk1(
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localparam FW_RAM_FIRST = 32'hd0000000;
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localparam FW_RAM_LAST = 32'hd00007ff;
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localparam ROM_PREFIX = 2'h0;
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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@ -156,6 +158,8 @@ module tk1(
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reg force_trap_reg;
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reg force_trap_set;
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reg spi_access_ok;
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//----------------------------------------------------------------
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// Wires.
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@ -223,13 +227,13 @@ module tk1(
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.clk(clk),
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.reset_n(reset_n),
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.spi_ss(spi_ss),
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.spi_sck(spi_sck),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso),
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.spi_ss((spi_ss & ~spi_access_ok)),
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.spi_sck((spi_sck & spi_access_ok)),
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.spi_mosi((spi_mosi & spi_access_ok)),
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.spi_miso((spi_miso & spi_access_ok)),
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.spi_enable(spi_enable),
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.spi_enable_vld(spi_enable_vld),
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.spi_enable((spi_enable & spi_access_ok)),
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.spi_enable_vld((spi_enable_vld & spi_access_ok)),
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.spi_start(spi_start),
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.spi_tx_data(spi_tx_data),
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.spi_tx_data_vld(spi_tx_data_vld),
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@ -373,6 +377,23 @@ module tk1(
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end
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//----------------------------------------------------------------
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// spi_access_control
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//
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// Logic thar controls if any access to the SPI master is done
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// by FW-code.
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//----------------------------------------------------------------
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always @*
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begin : spi_access_control
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if ((cpu_valid & cpu_instr) & (cpu_addr[31 : 30] == ROM_PREFIX)) begin
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spi_access_ok = 1'h1;
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end
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else begin
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spi_access_ok = 1'h0;
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end
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end
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//----------------------------------------------------------------
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// security_monitor
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//
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