Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-01-31 17:53:30 -05:00
Code Issues Packages Projects Releases Wiki Activity

Remove DONE state that added one extra final cycle

Browse Source
This commit is contained in:
Joachim Strömbergson 2022-10-12 10:06:41 +02:00
parent 24cf80af32
commit 82a64f2b2c
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
1 changed files with 13 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
hw/application_fpga/core/timer/rtl/timer_core.v
View File

@ -34,7 +34,6 @@ module timer_core(
localparam CTRL_IDLE = 2'h0; localparam CTRL_IDLE = 2'h0;
localparam CTRL_PRESCALER = 2'h1; localparam CTRL_PRESCALER = 2'h1;
localparam CTRL_TIMER = 2'h2; localparam CTRL_TIMER = 2'h2;
localparam CTRL_DONE = 2'h3;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -169,14 +168,18 @@ module timer_core(
CTRL_PRESCALER: begin CTRL_PRESCALER: begin
if (stop) begin if (stop) begin
core_ctrl_new = CTRL_DONE; ready_new = 1'h1;
ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end end
else begin else begin
if (prescaler_reg == 0) begin if (prescaler_reg == 0) begin
core_ctrl_new = CTRL_TIMER; core_ctrl_new = CTRL_TIMER;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end end
else begin else begin
prescaler_dec = 1'h1; prescaler_dec = 1'h1;
end end
@ -186,14 +189,20 @@ module timer_core(
CTRL_TIMER: begin CTRL_TIMER: begin
if (stop) begin if (stop) begin
core_ctrl_new = CTRL_DONE; ready_new = 1'h1;
ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end end
else begin else begin
if (timer_reg == 0) begin if (timer_reg == 0) begin
core_ctrl_new = CTRL_DONE; ready_new = 1'h1;
ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end end
else begin else begin
prescaler_set = 1'h1; prescaler_set = 1'h1;
timer_dec = 1'h1; timer_dec = 1'h1;
@ -203,14 +212,6 @@ module timer_core(
end end
end end
CTRL_DONE: begin
ready_new = 1'h1;
ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1;
end
default: begin default: begin
end end
endcase // case (core_ctrl_reg) endcase // case (core_ctrl_reg)