Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-08-05 21:24:11 -04:00
Code Issues Projects Releases Packages Wiki Activity

Feed CPU illegal instruction to trigger trap

Browse source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-02-28 16:17:27 +01:00 • committed by Daniel Lublin
parent 8ba97e16f3
commit 7612d00ccf
No known key found for this signature in database
GPG key ID: 75BD0FEB8D3E7830
2 changed files with 12 additions and 26 deletions
Download patch file Download diff file Expand all files Collapse all files

25
hw/application_fpga/core/tk1/rtl/tk1.v
View file

@ -23,8 +23,7 @@ module tk1(
input wire [31 : 0] cpu_addr, input wire [31 : 0] cpu_addr,
input wire cpu_instr, input wire cpu_instr,
input wire cpu_valid, input wire cpu_valid,
output wire force_jump, output wire force_trap,
output wire [31 : 0] jump_instr,
output wire led_r, output wire led_r,
output wire led_g, output wire led_g,
@ -79,7 +78,6 @@ module tk1(
localparam ADDR_CPU_MON_CTRL = 8'h60; localparam ADDR_CPU_MON_CTRL = 8'h60;
localparam ADDR_CPU_MON_FIRST = 8'h61; localparam ADDR_CPU_MON_FIRST = 8'h61;
localparam ADDR_CPU_MON_LAST = 8'h62; localparam ADDR_CPU_MON_LAST = 8'h62;
localparam ADDR_CPU_MON_INSTR = 8'h63;
localparam TK1_NAME0 = 32'h746B3120; // "tk1 " localparam TK1_NAME0 = 32'h746B3120; // "tk1 "
localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf" localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf"
@ -129,8 +127,6 @@ module tk1(
reg cpu_mon_first_we; reg cpu_mon_first_we;
reg [31 : 0] cpu_mon_last_reg; reg [31 : 0] cpu_mon_last_reg;
reg cpu_mon_last_we; reg cpu_mon_last_we;
reg [31 : 0] cpu_mon_instr_reg;
reg cpu_mon_instr_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -139,7 +135,7 @@ module tk1(
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
reg [31 : 0] tmp_read_data; reg [31 : 0] tmp_read_data;
reg tmp_ready; reg tmp_ready;
reg tmp_force_jump; reg tmp_force_trap;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg [2 : 0] muxed_led; reg [2 : 0] muxed_led;
@ -153,8 +149,7 @@ module tk1(
assign fw_app_mode = switch_app_reg; assign fw_app_mode = switch_app_reg;
assign force_jump = tmp_force_jump; assign force_trap = tmp_force_trap;
assign jump_instr = cpu_mon_instr_reg;
assign gpio3 = gpio3_reg; assign gpio3 = gpio3_reg;
assign gpio4 = gpio4_reg; assign gpio4 = gpio4_reg;
@ -210,7 +205,6 @@ module tk1(
cpu_mon_en_reg <= 1'h0; cpu_mon_en_reg <= 1'h0;
cpu_mon_first_reg <= 32'h0; cpu_mon_first_reg <= 32'h0;
cpu_mon_last_reg <= 32'h0; cpu_mon_last_reg <= 32'h0;
cpu_mon_instr_reg <= 32'h0;
end end
else begin else begin
@ -269,10 +263,6 @@ module tk1(
if (cpu_mon_last_we) begin if (cpu_mon_last_we) begin
cpu_mon_last_reg <= write_data; cpu_mon_last_reg <= write_data;
end end
if (cpu_mon_instr_we) begin
cpu_mon_instr_reg <= write_data;
end
end end
end // reg_update end // reg_update
@ -305,13 +295,13 @@ module tk1(
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @*
begin : cpu_monitor begin : cpu_monitor
tmp_force_jump = 1'h0; tmp_force_trap = 1'h0;
if (cpu_mon_en_reg) begin if (cpu_mon_en_reg) begin
if (cpu_valid && cpu_instr) begin if (cpu_valid && cpu_instr) begin
if ((cpu_addr >= cpu_mon_first_reg) && if ((cpu_addr >= cpu_mon_first_reg) &&
(cpu_addr <= cpu_mon_last_reg)) begin (cpu_addr <= cpu_mon_last_reg)) begin
tmp_force_jump = 1'h1; tmp_force_trap = 1'h1;
end end
end end
end end
@ -335,7 +325,6 @@ module tk1(
cpu_mon_en_we = 1'h0; cpu_mon_en_we = 1'h0;
cpu_mon_first_we = 1'h0; cpu_mon_first_we = 1'h0;
cpu_mon_last_we = 1'h0; cpu_mon_last_we = 1'h0;
cpu_mon_instr_we = 1'h0;
cpu_mon_en_we = 1'h0; cpu_mon_en_we = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;
tmp_ready = 1'h0; tmp_ready = 1'h0;
@ -391,10 +380,6 @@ module tk1(
if (address == ADDR_CPU_MON_LAST) begin if (address == ADDR_CPU_MON_LAST) begin
cpu_mon_last_we = 1'h1; cpu_mon_last_we = 1'h1;
end end
if (address == ADDR_CPU_MON_INSTR) begin
cpu_mon_instr_we = 1'h1;
end
end end
else begin else begin

13
hw/application_fpga/rtl/application_fpga.v
View file

@ -51,6 +51,9 @@ module application_fpga(
localparam FW_RAM_PREFIX = 6'h10; localparam FW_RAM_PREFIX = 6'h10;
localparam TK1_PREFIX = 6'h3f; localparam TK1_PREFIX = 6'h3f;
// Instruction used to cause a trap.
localparam ILLEGAL_INSTRUCTION = 32'h0;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers, memories with associated wires. // Registers, memories with associated wires.
@ -151,8 +154,7 @@ module application_fpga(
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire fw_app_mode; wire fw_app_mode;
wire force_jump; wire force_trap;
wire [31 : 0] jump_instr;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -320,8 +322,7 @@ module application_fpga(
.cpu_addr(cpu_addr), .cpu_addr(cpu_addr),
.cpu_instr(cpu_instr), .cpu_instr(cpu_instr),
.cpu_valid(cpu_valid), .cpu_valid(cpu_valid),
.force_jump(force_jump), .force_trap(force_trap),
.jump_instr(jump_instr),
.led_r(led_r), .led_r(led_r),
.led_g(led_g), .led_g(led_g),
@ -415,8 +416,8 @@ module application_fpga(
tk1_write_data = cpu_wdata; tk1_write_data = cpu_wdata;
if (cpu_valid && !muxed_ready_reg) begin if (cpu_valid && !muxed_ready_reg) begin
if (force_jump) begin if (force_trap) begin
muxed_rdata_new = jump_instr; muxed_rdata_new = ILLEGAL_INSTRUCTION;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
else begin else begin