diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
index dec6df3..0dc7af1 100644
--- a/hw/application_fpga/Makefile
+++ b/hw/application_fpga/Makefile
@@ -261,7 +261,8 @@ LINT_FLAGS = \
 	-Wno-WIDTHEXPAND \
 	-Wno-UNOPTFLAT \
 	--timescale 1ns/1ns \
-	-DNO_ICE40_DEFAULT_ASSIGNMENTS
+	-DNO_ICE40_DEFAULT_ASSIGNMENTS \
+	-Wno-GENUNNAMED
 
 lint: $(FPGA_VERILOG_SRCS) \
 		$(SIM_VERILOG_SRCS) \