From 71d091fcd5c6e621cab4c76554e5695fae33c681 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 29 Jan 2024 13:50:45 +0100 Subject: [PATCH] Add tx debug port functionality with API controlled select --- hw/application_fpga/core/uart/rtl/uart.v | 49 +++++++++++++++++++++- hw/application_fpga/core/uart/tb/tb_uart.v | 6 ++- hw/application_fpga/fw/tk1_mem.h | 1 + hw/application_fpga/rtl/application_fpga.v | 3 +- 4 files changed, 55 insertions(+), 4 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v index b2d0364..e7a9592 100644 --- a/hw/application_fpga/core/uart/rtl/uart.v +++ b/hw/application_fpga/core/uart/rtl/uart.v @@ -54,6 +54,7 @@ module uart( input wire rxd, output wire txd, + output wire txd_debug, input wire cs, input wire we, @@ -72,6 +73,7 @@ module uart( localparam ADDR_BIT_RATE = 8'h10; localparam ADDR_DATA_BITS = 8'h11; localparam ADDR_STOP_BITS = 8'h12; + localparam ADDR_TX_SELECT = 8'h18; localparam ADDR_RX_STATUS = 8'h20; localparam ADDR_RX_DATA = 8'h21; @@ -90,6 +92,9 @@ module uart( localparam DEFAULT_DATA_BITS = 4'h8; localparam DEFAULT_STOP_BITS = 2'h1; + // By default send UART tx to the normal UART pin. + localparam DEFAULT_TX_SELECT = 1'h0; + //---------------------------------------------------------------- // Registers including update variables and write enable. @@ -103,6 +108,9 @@ module uart( reg [1 : 0] stop_bits_reg; reg stop_bits_we; + reg tx_select_reg; + reg tx_select_we; + //---------------------------------------------------------------- // Wires. @@ -123,12 +131,18 @@ module uart( reg [31 : 0] tmp_read_data; reg tmp_ready; + wire txd_internal; + reg tmp_txd; + reg tmp_txd_debug; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign read_data = tmp_read_data; assign ready = tmp_ready; + assign txd = tmp_txd; + assign txd_debug = tmp_txd_debug; //---------------------------------------------------------------- @@ -145,7 +159,7 @@ module uart( // External data interface .rxd(rxd), - .txd(txd), + .txd(txd_internal), // Internal receive interface. .rxd_syn(core_rxd_syn), @@ -188,6 +202,7 @@ module uart( bit_rate_reg <= DEFAULT_BIT_RATE; data_bits_reg <= DEFAULT_DATA_BITS; stop_bits_reg <= DEFAULT_STOP_BITS; + tx_select_reg <= DEFAULT_TX_SELECT; end else begin if (bit_rate_we) begin @@ -201,9 +216,30 @@ module uart( if (stop_bits_we) begin stop_bits_reg <= write_data[1 : 0]; end + + if (tx_select_we) begin + tx_select_reg <= write_data[0]; + end end end // reg_update + //---------------------------------------------------------------- + // tx_select + // + // Logic that selects which pin tx data should be sent to. + //---------------------------------------------------------------- + always @* + begin: tx_select + if (tx_select_reg) begin + tmp_txd = 1'h0; + tmp_txd_debug = txd_internal; + + end else begin + tmp_txd = txd_internal; + tmp_txd_debug = 1'h0; + end + end + //---------------------------------------------------------------- // api @@ -219,6 +255,7 @@ module uart( stop_bits_we = 1'h0; core_txd_syn = 1'h0; fifo_out_ack = 1'h0; + tx_select_we = 1'h0; tmp_read_data = 32'h0; tmp_ready = 1'h0; @@ -241,6 +278,12 @@ module uart( stop_bits_we = 1; end + ADDR_TX_SELECT: begin + if (core_txd_ready) begin + tx_select_we = 1'h1; + end + end + ADDR_TX_DATA: begin if (core_txd_ready) begin core_txd_syn = 1'h1; @@ -266,6 +309,10 @@ module uart( tmp_read_data = {30'h0, stop_bits_reg}; end + ADDR_TX_SELECT: begin + tmp_read_data = {31'h0, tx_select_reg}; + end + ADDR_RX_STATUS: begin tmp_read_data = {31'h0, fifo_out_syn}; end diff --git a/hw/application_fpga/core/uart/tb/tb_uart.v b/hw/application_fpga/core/uart/tb/tb_uart.v index a8afb28..eb2a135 100644 --- a/hw/application_fpga/core/uart/tb/tb_uart.v +++ b/hw/application_fpga/core/uart/tb/tb_uart.v @@ -59,6 +59,7 @@ module tb_uart(); reg tb_reset_n; reg tb_rxd; wire tb_txd; + wire tb_txd_debug; reg tb_cs; reg tb_we; reg [7 : 0] tb_address; @@ -78,6 +79,7 @@ module tb_uart(); .rxd(tb_rxd), .txd(tb_txd), + .txd_debug(tb_txd_debug), // API interface. .cs(tb_cs), @@ -156,8 +158,8 @@ module tb_uart(); $display("State of DUT"); $display("------------"); $display("Inputs and outputs:"); - $display("rxd = 0x%01x, txd = 0x%01x,", - dut.core.rxd, dut.core.txd); + $display("rxd = 0x%01x, txd = 0x%01x, txd_debug = 0x%01x", + dut.rxd, dut.txd, dut.txd_debug); $display(""); $display("Sample and data registers:"); diff --git a/hw/application_fpga/fw/tk1_mem.h b/hw/application_fpga/fw/tk1_mem.h index f75af52..6000e22 100644 --- a/hw/application_fpga/fw/tk1_mem.h +++ b/hw/application_fpga/fw/tk1_mem.h @@ -60,6 +60,7 @@ enum { TK1_MMIO_UART_BIT_RATE = TK1_MMIO_UART_BASE | 0x40, TK1_MMIO_UART_DATA_BITS = TK1_MMIO_UART_BASE | 0x44, TK1_MMIO_UART_STOP_BITS = TK1_MMIO_UART_BASE | 0x48, + TK1_MMIO_UART_TX_SELECT = TK1_MMIO_UART_BASE | 0x60, TK1_MMIO_UART_RX_STATUS = TK1_MMIO_UART_BASE | 0x80, TK1_MMIO_UART_RX_DATA = TK1_MMIO_UART_BASE | 0x84, TK1_MMIO_UART_RX_BYTES = TK1_MMIO_UART_BASE | 0x88, diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v index e02a15f..9afc9c9 100644 --- a/hw/application_fpga/rtl/application_fpga.v +++ b/hw/application_fpga/rtl/application_fpga.v @@ -290,6 +290,7 @@ module application_fpga( .rxd(interface_tx), .txd(interface_rx), + .txd_debug(app_gpio4), .cs(uart_cs), .we(uart_we), @@ -336,7 +337,7 @@ module application_fpga( .gpio1(app_gpio1), .gpio2(app_gpio2), .gpio3(app_gpio3), - .gpio4(app_gpio4), + .gpio4(), .cs(tk1_cs), .we(tk1_we),