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Fix bug in timer core, where it misses clock cycles

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Remove redundant timer state. This fixes a bug where the timer misses a
clock cycle every time the prescaler counter reaches 1. This means if
one uses a large prescaler, like 18E6, it is barely noticeable, but if
one have a low prescaler and a high timer value it becomes significant.
This also yields the running_* registers redundant, which are removed.

Add clarity to the readme.

Update the timer to default to values of one, for prescaler and timer
count.
This commit is contained in:
Daniel Jobson 2024-11-22 13:03:45 +01:00
parent 3d7a97ecbc
commit 6bdedf4f86
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GPG key ID: 3707A9DBF4BB8F1A
4 changed files with 45 additions and 75 deletions
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hw/application_fpga/application_fpga.bin.sha256
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d5e4153187d1808b77535c9233a28073de7eeed4ead373efa9d7dd835833b03a application_fpga.bin
2a3928e8587c8d5d7eca6048c6448dc1d16d52a9a25d3ca5026bec3e7fb14ef3 application_fpga.bin