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PoC: Control access to FW RAM

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Allow FW RAM access only in the following execution contexts:
- Firmware mode
- IRQ_SYSCALL_HI

Input port `system_mode` of the `fw_ram` module is replaced with an
enable port. Since access to FW RAM not longer depend only on
system_mode
This commit is contained in:
Mikael Ågren 2024-12-11 14:29:04 +01:00
parent a871d23d5d
commit 62dba7c4fe
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GPG key ID: E02DA3D397792C46
7 changed files with 92 additions and 37 deletions
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6
hw/application_fpga/tb/application_fpga_sim.v
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@ -147,6 +147,7 @@ module application_fpga_sim (
reg [31 : 0] fw_ram_write_data;
wire [31 : 0] fw_ram_read_data;
wire fw_ram_ready;
wire fw_ram_en;
reg touch_sense_cs;
reg touch_sense_we;
@ -268,8 +269,7 @@ module application_fpga_sim (
.clk(clk),
.reset_n(reset_n),
.system_mode(system_mode),
.en(fw_ram_en),
.cs(fw_ram_cs),
.we(fw_ram_we),
.address(fw_ram_address),
@ -383,6 +383,8 @@ module application_fpga_sim (
.access_level_hi (irq31_eoi),
.access_level_med(irq30_eoi),
.fw_ram_en(fw_ram_en),
.cs(tk1_cs),
.we(tk1_we),
.address(tk1_address),

2
hw/application_fpga/tb/tb_application_fpga_sim.v
View file

@ -80,7 +80,7 @@ module tb_application_fpga_sim ();
//----------------------------------------------------------------
initial begin
// End simulation after XXX time units (set by timescale)
#1600;
#3000;
$display("TIMEOUT");
$finish;
end