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FPGA: Add labels for generate statements
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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@ -271,7 +271,7 @@ module picorv32 #(
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reg pcpi_int_wait;
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reg pcpi_int_ready;
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generate if (ENABLE_FAST_MUL) begin
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generate if (ENABLE_FAST_MUL) begin : gen_fast_mul
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picorv32_pcpi_fast_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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@ -284,7 +284,7 @@ module picorv32 #(
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.pcpi_wait (pcpi_mul_wait ),
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.pcpi_ready(pcpi_mul_ready )
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);
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end else if (ENABLE_MUL) begin
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end else if (ENABLE_MUL) begin : gen_mul
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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@ -297,14 +297,14 @@ module picorv32 #(
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.pcpi_wait (pcpi_mul_wait ),
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.pcpi_ready(pcpi_mul_ready )
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);
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end else begin
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end else begin : gen_no_mul
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assign pcpi_mul_wr = 0;
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assign pcpi_mul_rd = 32'bx;
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assign pcpi_mul_wait = 0;
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assign pcpi_mul_ready = 0;
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end endgenerate
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generate if (ENABLE_DIV) begin
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generate if (ENABLE_DIV) begin : gen_div
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picorv32_pcpi_div pcpi_div (
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.clk (clk ),
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.resetn (resetn ),
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@ -317,7 +317,7 @@ module picorv32 #(
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.pcpi_wait (pcpi_div_wait ),
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.pcpi_ready(pcpi_div_ready )
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);
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end else begin
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end else begin : gen_no_div
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assign pcpi_div_wr = 0;
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assign pcpi_div_rd = 32'bx;
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assign pcpi_div_wait = 0;
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@ -1230,7 +1230,7 @@ module picorv32 #(
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reg [31:0] alu_shl, alu_shr;
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reg alu_eq, alu_ltu, alu_lts;
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generate if (TWO_CYCLE_ALU) begin
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generate if (TWO_CYCLE_ALU) begin : gen_two_cycle_alu
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always @(posedge clk) begin
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alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
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alu_eq <= reg_op1 == reg_op2;
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@ -1239,7 +1239,7 @@ module picorv32 #(
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alu_shl <= reg_op1 << reg_op2[4:0];
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alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
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end
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end else begin
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end else begin : gen_single_cycle_alu
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always @* begin
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alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
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alu_eq = reg_op1 == reg_op2;
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