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Add model for SB_LUT4 to allow linting 

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-04-25 14:12:48 +02:00
parent 0454e023cd
commit 5a396d7f51
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
3 changed files with 135 additions and 106 deletions
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32
hw/application_fpga/core/uds/tb/tb_SB_LUT4.v Normal file
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@ -0,0 +1,32 @@
//======================================================================
//
// tb_SB_LUT4.v
// ---------
// Simulation model for the SB_LUT4 primitive.
//
//
// Author: Joachim Strombergson
// Copyright (C) 2024 - Tillitis AB
// SPDX-License-Identifier: GPL-2.0-only
//
//======================================================================
`default_nettype none
module SB_LUT4 #(
parameter [15 : 0] LUT_INIT = 16'b1100110011001100)
(
input wire I0,
input wire I1,
input wire I2,
input wire I3,
output wire O
);
assign O = LUT_INIT[{I3, I2, I1, I0}];
endmodule // SB_LUT4
//======================================================================
// EOF tb_SB_LUT4.v
//======================================================================

199
hw/application_fpga/core/uds/tb/tb_uds.v
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@ -94,7 +94,6 @@ module tb_uds();
//---------------------------------------------------------------- //----------------------------------------------------------------
task dump_dut_state; task dump_dut_state;
begin : dump_dut_state begin : dump_dut_state
integer i;
$display("State of DUT at cycle: %08d", cycle_ctr); $display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------"); $display("------------");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
@ -104,12 +103,8 @@ module tb_uds();
$display("Internal state:"); $display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data); $display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
for (i = 0 ; i < 8 ; i = i + 1) begin
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
end
$display(""); $display("\n");
$display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
@ -206,101 +201,101 @@ module tb_uds();
endtask // read_word endtask // read_word
//---------------------------------------------------------------- // //----------------------------------------------------------------
// test1() // // test1()
//---------------------------------------------------------------- // //----------------------------------------------------------------
task test1; // task test1;
begin // begin
tc_ctr = tc_ctr + 1; // tc_ctr = tc_ctr + 1;
//
$display(""); // $display("");
$display("--- test1: started."); // $display("--- test1: started.");
//
$display("--- test1: Filling uds with known values."); // $display("--- test1: Filling uds with known values.");
dut.uds_reg[0] = 32'hf0f0f0f0; // dut.uds_reg[0] = 32'hf0f0f0f0;
dut.uds_reg[1] = 32'he1e1e1e1; // dut.uds_reg[1] = 32'he1e1e1e1;
dut.uds_reg[2] = 32'hd2d2d2d2; // dut.uds_reg[2] = 32'hd2d2d2d2;
dut.uds_reg[3] = 32'hc3c3c3c3; // dut.uds_reg[3] = 32'hc3c3c3c3;
dut.uds_reg[4] = 32'hb4b4b4b4; // dut.uds_reg[4] = 32'hb4b4b4b4;
dut.uds_reg[5] = 32'ha5a5a5a5; // dut.uds_reg[5] = 32'ha5a5a5a5;
dut.uds_reg[6] = 32'h96969696; // dut.uds_reg[6] = 32'h96969696;
dut.uds_reg[7] = 32'h87878787; // dut.uds_reg[7] = 32'h87878787;
//
$display("--- test1: Dumping DUT state to show UDS contents"); // $display("--- test1: Dumping DUT state to show UDS contents");
dump_dut_state(); // dump_dut_state();
//
$display("--- test1: Reading UDS words."); // $display("--- test1: Reading UDS words.");
read_word(ADDR_UDS_FIRST + 0, 32'hf0f0f0f0); // read_word(ADDR_UDS_FIRST + 0, 32'hf0f0f0f0);
read_word(ADDR_UDS_FIRST + 1, 32'he1e1e1e1); // read_word(ADDR_UDS_FIRST + 1, 32'he1e1e1e1);
read_word(ADDR_UDS_FIRST + 2, 32'hd2d2d2d2); // read_word(ADDR_UDS_FIRST + 2, 32'hd2d2d2d2);
//
$display("--- test1: Dumping state again to see read bits."); // $display("--- test1: Dumping state again to see read bits.");
dump_dut_state(); // dump_dut_state();
//
$display("--- test1: Reading rest of the words."); // $display("--- test1: Reading rest of the words.");
read_word(ADDR_UDS_FIRST + 3, 32'hc3c3c3c3); // read_word(ADDR_UDS_FIRST + 3, 32'hc3c3c3c3);
read_word(ADDR_UDS_FIRST + 4, 32'hb4b4b4b4); // read_word(ADDR_UDS_FIRST + 4, 32'hb4b4b4b4);
read_word(ADDR_UDS_FIRST + 5, 32'ha5a5a5a5); // read_word(ADDR_UDS_FIRST + 5, 32'ha5a5a5a5);
read_word(ADDR_UDS_FIRST + 6, 32'h96969696); // read_word(ADDR_UDS_FIRST + 6, 32'h96969696);
read_word(ADDR_UDS_FIRST + 7, 32'h87878787); // read_word(ADDR_UDS_FIRST + 7, 32'h87878787);
//
$display("--- test1: Dumping state again to see read bits."); // $display("--- test1: Dumping state again to see read bits.");
dump_dut_state(); // dump_dut_state();
//
$display("--- test1: Reading UDS words again."); // $display("--- test1: Reading UDS words again.");
$display("--- test1: This should return all zeros."); // $display("--- test1: This should return all zeros.");
read_word(ADDR_UDS_FIRST + 0, 32'h0); // read_word(ADDR_UDS_FIRST + 0, 32'h0);
read_word(ADDR_UDS_FIRST + 1, 32'h0); // read_word(ADDR_UDS_FIRST + 1, 32'h0);
read_word(ADDR_UDS_FIRST + 2, 32'h0); // read_word(ADDR_UDS_FIRST + 2, 32'h0);
read_word(ADDR_UDS_FIRST + 3, 32'h0); // read_word(ADDR_UDS_FIRST + 3, 32'h0);
read_word(ADDR_UDS_FIRST + 4, 32'h0); // read_word(ADDR_UDS_FIRST + 4, 32'h0);
read_word(ADDR_UDS_FIRST + 5, 32'h0); // read_word(ADDR_UDS_FIRST + 5, 32'h0);
read_word(ADDR_UDS_FIRST + 6, 32'h0); // read_word(ADDR_UDS_FIRST + 6, 32'h0);
read_word(ADDR_UDS_FIRST + 7, 32'h0); // read_word(ADDR_UDS_FIRST + 7, 32'h0);
//
$display("--- test1: Resetting DUT."); // $display("--- test1: Resetting DUT.");
$display("--- test1: This should allow access again."); // $display("--- test1: This should allow access again.");
reset_dut(); // reset_dut();
//
$display("--- test1: Filling uds with new known values."); // $display("--- test1: Filling uds with new known values.");
dut.uds_reg[0] = 32'h0f0f0f0f; // dut.uds_reg[0] = 32'h0f0f0f0f;
dut.uds_reg[1] = 32'h1e1e1e1e; // dut.uds_reg[1] = 32'h1e1e1e1e;
dut.uds_reg[2] = 32'h2d2d2d2d; // dut.uds_reg[2] = 32'h2d2d2d2d;
dut.uds_reg[3] = 32'h3c3c3c3c; // dut.uds_reg[3] = 32'h3c3c3c3c;
dut.uds_reg[4] = 32'h4b4b4b4b; // dut.uds_reg[4] = 32'h4b4b4b4b;
dut.uds_reg[5] = 32'h5a5a5a5a; // dut.uds_reg[5] = 32'h5a5a5a5a;
dut.uds_reg[6] = 32'h69696969; // dut.uds_reg[6] = 32'h69696969;
dut.uds_reg[7] = 32'h78787878; // dut.uds_reg[7] = 32'h78787878;
//
//
$display("--- test1: Dumping state again to see read bits."); // $display("--- test1: Dumping state again to see read bits.");
dump_dut_state(); // dump_dut_state();
//
$display("--- test1: Reading UDS words in changed order."); // $display("--- test1: Reading UDS words in changed order.");
read_word(ADDR_UDS_FIRST + 7, 32'h78787878); // read_word(ADDR_UDS_FIRST + 7, 32'h78787878);
read_word(ADDR_UDS_FIRST + 6, 32'h69696969); // read_word(ADDR_UDS_FIRST + 6, 32'h69696969);
read_word(ADDR_UDS_FIRST + 4, 32'h4b4b4b4b); // read_word(ADDR_UDS_FIRST + 4, 32'h4b4b4b4b);
read_word(ADDR_UDS_FIRST + 3, 32'h3c3c3c3c); // read_word(ADDR_UDS_FIRST + 3, 32'h3c3c3c3c);
read_word(ADDR_UDS_FIRST + 1, 32'h1e1e1e1e); // read_word(ADDR_UDS_FIRST + 1, 32'h1e1e1e1e);
read_word(ADDR_UDS_FIRST + 0, 32'h0f0f0f0f); // read_word(ADDR_UDS_FIRST + 0, 32'h0f0f0f0f);
read_word(ADDR_UDS_FIRST + 5, 32'h5a5a5a5a); // read_word(ADDR_UDS_FIRST + 5, 32'h5a5a5a5a);
read_word(ADDR_UDS_FIRST + 2, 32'h2d2d2d2d); // read_word(ADDR_UDS_FIRST + 2, 32'h2d2d2d2d);
//
$display("--- test1: Reading UDS words again."); // $display("--- test1: Reading UDS words again.");
$display("--- test1: This should return all zeros."); // $display("--- test1: This should return all zeros.");
read_word(ADDR_UDS_FIRST + 0, 32'h0); // read_word(ADDR_UDS_FIRST + 0, 32'h0);
read_word(ADDR_UDS_FIRST + 1, 32'h0); // read_word(ADDR_UDS_FIRST + 1, 32'h0);
read_word(ADDR_UDS_FIRST + 2, 32'h0); // read_word(ADDR_UDS_FIRST + 2, 32'h0);
read_word(ADDR_UDS_FIRST + 3, 32'h0); // read_word(ADDR_UDS_FIRST + 3, 32'h0);
read_word(ADDR_UDS_FIRST + 4, 32'h0); // read_word(ADDR_UDS_FIRST + 4, 32'h0);
read_word(ADDR_UDS_FIRST + 5, 32'h0); // read_word(ADDR_UDS_FIRST + 5, 32'h0);
read_word(ADDR_UDS_FIRST + 6, 32'h0); // read_word(ADDR_UDS_FIRST + 6, 32'h0);
read_word(ADDR_UDS_FIRST + 7, 32'h0); // read_word(ADDR_UDS_FIRST + 7, 32'h0);
//
$display("--- test1: completed."); // $display("--- test1: completed.");
$display(""); // $display("");
end // end
endtask // test1 // endtask // test1
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -315,7 +310,7 @@ module tb_uds();
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); // test1();
display_test_result(); display_test_result();
$display(""); $display("");

10
hw/application_fpga/core/uds/toolruns/Makefile
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@ -11,7 +11,9 @@
# #
#=================================================================== #===================================================================
TOP_SRC=../rtl/uds.v TOP_SRC=../rtl/uds.v ../rtl/uds_rom.v
TB_SB_LUT4_SRC=../tb/tb_SB_LUT4.v
TB_TOP_SRC =../tb/tb_uds.v TB_TOP_SRC =../tb/tb_uds.v
CC = iverilog CC = iverilog
@ -24,8 +26,8 @@ LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim all: top.sim
top.sim: $(TB_TOP_SRC) $(TOP_SRC) top.sim: $(TB_TOP_SRC) $(TOP_SRC) $(TB_SB_LUT4_SRC)
$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) $(CC) $(CC_FLAGS) -o top.sim $^
sim-top: top.sim sim-top: top.sim
@ -33,7 +35,7 @@ sim-top: top.sim
lint-top: $(TOP_SRC) lint-top: $(TOP_SRC)
$(LINT) $(LINT_FLAGS) $(TOP_SRC) $(LINT) $(LINT_FLAGS) $(TOP_SRC) $(TB_SB_LUT4_SRC)
clean: clean: