Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-01-23 05:41:05 -05:00
Code Issues Packages Projects Releases Wiki Activity

fpga: Add API to enable and disable SPI access

Browse Source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-07-10 14:31:12 +02:00 committed by Daniel Jobson
parent 12251839f0
commit 556f582eec
No known key found for this signature in database
GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 18 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
hw/application_fpga/core/tk1/rtl/tk1.v
View File

@ -105,6 +105,8 @@ module tk1(
localparam ADDR_SPI_DATA = 8'h82; localparam ADDR_SPI_DATA = 8'h82;
`endif // INCLUDE_SPI_MASTER `endif // INCLUDE_SPI_MASTER
localparam ADDR_ACCESS_CTRL = 8'h83;
localparam TK1_NAME0 = 32'h746B3120; // "tk1 " localparam TK1_NAME0 = 32'h746B3120; // "tk1 "
localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf" localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf"
localparam TK1_VERSION = 32'h00000005; localparam TK1_VERSION = 32'h00000005;
@ -166,7 +168,6 @@ module tk1(
reg force_trap_set; reg force_trap_set;
reg access_ok_reg; reg access_ok_reg;
reg access_ok_new;
reg access_ok_we; reg access_ok_we;
@ -367,7 +368,7 @@ module tk1(
end end
if (access_ok_we) begin if (access_ok_we) begin
access_ok_reg <= access_ok_new; access_ok_reg <= write_data[0];
end end
end end
end // reg_update end // reg_update
@ -396,29 +397,6 @@ module tk1(
end end
//----------------------------------------------------------------
// access_control
//
// Logic that controls access to resources that only FW (ROM),
// not applications should be allowed to use.
//----------------------------------------------------------------
always @*
begin : access_control
access_ok_new = 1'h0;
access_ok_we = 1'h0;
if (rom_access) begin
access_ok_new = 1'h1;
access_ok_we = 1'h1;
end
if (ram_access) begin
access_ok_new = 1'h0;
access_ok_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// security_monitor // security_monitor
// //
@ -482,14 +460,16 @@ module tk1(
cpu_mon_en_we = 1'h0; cpu_mon_en_we = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;
tmp_ready = 1'h0; tmp_ready = 1'h0;
access_ok_we = 1'h0;
`ifdef INCLUDE_SPI_MASTER `ifdef INCLUDE_SPI_MASTER
spi_enable_vld = 1'h0; spi_enable_vld = 1'h0;
spi_start = 1'h0; spi_start = 1'h0;
spi_tx_data_vld = 1'h0; spi_tx_data_vld = 1'h0;
spi_enable = write_data[0]; spi_enable = write_data[0] & access_ok_reg;
spi_tx_data = write_data[7 : 0]; spi_tx_data = write_data[7 : 0] & {8{access_ok_reg}};
`endif // INCLUDE_SPI_MASTER `endif // INCLUDE_SPI_MASTER
if (cs) begin if (cs) begin
@ -564,6 +544,11 @@ module tk1(
end end
end end
if (address == ADDR_ACCESS_CTRL) begin
access_ok_we = 1'h1;
end
`ifdef INCLUDE_SPI_MASTER `ifdef INCLUDE_SPI_MASTER
if (address == ADDR_SPI_EN) begin if (address == ADDR_SPI_EN) begin
spi_enable_vld = 1'h1; spi_enable_vld = 1'h1;
@ -629,11 +614,15 @@ module tk1(
`ifdef INCLUDE_SPI_MASTER `ifdef INCLUDE_SPI_MASTER
if (address == ADDR_SPI_XFER) begin if (address == ADDR_SPI_XFER) begin
tmp_read_data[0] = spi_ready & access_ok_reg; if (access_ok_reg) begin
tmp_read_data[0] = spi_ready;
end
end end
if (address == ADDR_SPI_DATA) begin if (address == ADDR_SPI_DATA) begin
tmp_read_data[7 : 0] = spi_rx_data & {8{access_ok_reg}}; if (access_ok_reg) begin
tmp_read_data[7 : 0] = spi_rx_data;
end
end end
`endif // INCLUDE_SPI_MASTER `endif // INCLUDE_SPI_MASTER