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https://github.com/tillitis/tillitis-key1.git
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fpga: Add API to enable and disable SPI access
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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@ -105,6 +105,8 @@ module tk1(
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localparam ADDR_SPI_DATA = 8'h82;
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`endif // INCLUDE_SPI_MASTER
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localparam ADDR_ACCESS_CTRL = 8'h83;
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localparam TK1_NAME0 = 32'h746B3120; // "tk1 "
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localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf"
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localparam TK1_VERSION = 32'h00000005;
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@ -166,7 +168,6 @@ module tk1(
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reg force_trap_set;
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reg access_ok_reg;
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reg access_ok_new;
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reg access_ok_we;
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@ -367,7 +368,7 @@ module tk1(
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end
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if (access_ok_we) begin
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access_ok_reg <= access_ok_new;
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access_ok_reg <= write_data[0];
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end
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end
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end // reg_update
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@ -396,29 +397,6 @@ module tk1(
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end
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//----------------------------------------------------------------
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// access_control
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//
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// Logic that controls access to resources that only FW (ROM),
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// not applications should be allowed to use.
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//----------------------------------------------------------------
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always @*
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begin : access_control
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access_ok_new = 1'h0;
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access_ok_we = 1'h0;
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if (rom_access) begin
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access_ok_new = 1'h1;
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access_ok_we = 1'h1;
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end
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if (ram_access) begin
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access_ok_new = 1'h0;
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access_ok_we = 1'h1;
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end
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end
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//----------------------------------------------------------------
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// security_monitor
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//
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@ -482,14 +460,16 @@ module tk1(
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cpu_mon_en_we = 1'h0;
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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access_ok_we = 1'h0;
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`ifdef INCLUDE_SPI_MASTER
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spi_enable_vld = 1'h0;
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spi_start = 1'h0;
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spi_tx_data_vld = 1'h0;
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spi_enable = write_data[0];
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spi_tx_data = write_data[7 : 0];
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spi_enable = write_data[0] & access_ok_reg;
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spi_tx_data = write_data[7 : 0] & {8{access_ok_reg}};
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`endif // INCLUDE_SPI_MASTER
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if (cs) begin
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@ -564,6 +544,11 @@ module tk1(
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end
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end
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if (address == ADDR_ACCESS_CTRL) begin
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access_ok_we = 1'h1;
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end
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`ifdef INCLUDE_SPI_MASTER
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if (address == ADDR_SPI_EN) begin
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spi_enable_vld = 1'h1;
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@ -629,11 +614,15 @@ module tk1(
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`ifdef INCLUDE_SPI_MASTER
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if (address == ADDR_SPI_XFER) begin
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tmp_read_data[0] = spi_ready & access_ok_reg;
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if (access_ok_reg) begin
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tmp_read_data[0] = spi_ready;
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end
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end
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if (address == ADDR_SPI_DATA) begin
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tmp_read_data[7 : 0] = spi_rx_data & {8{access_ok_reg}};
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if (access_ok_reg) begin
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tmp_read_data[7 : 0] = spi_rx_data;
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end
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end
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`endif // INCLUDE_SPI_MASTER
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