Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-12-15 08:38:53 -05:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'fw_ram'

Browse source
This commit is contained in:
Joachim Strömbergson 2022-10-13 13:16:53 +02:00
commit 51a22dc32c
5 changed files with 185 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

5
hw/application_fpga/Makefile
View file

@ -43,11 +43,11 @@ ASFLAGS = -target riscv32-unknown-none-elf -march=rv32imc -mabi=ilp32 -mno-relax
ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
# FPGA specific Verilog source files.
# FPGA specific source files.
FPGA_SRC = $(P)/rtl/application_fpga.v \
$(P)/rtl/clk_reset_gen.v
# Verilator simulation specific Verilog source files.
# Verilator simulation specific source files.
VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
$(P)/tb/reset_gen_vsim.v
@ -55,6 +55,7 @@ VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
VERILOG_SRCS = \
$(P)/rtl/ram.v \
$(P)/rtl/rom.v \
$(P)/rtl/fw_ram.v \
$(P)/core/picorv32/rtl/picorv32.v \
$(P)/core/timer/rtl/timer_core.v \
$(P)/core/timer/rtl/timer.v \