Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity

Add API functionality to disable CDI access

Browse Source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-04-15 13:30:54 +02:00 committed by Michael Cardell Widerkrantz
parent f655196af7
commit 4dbf31cc74
No known key found for this signature in database
GPG Key ID: D3DB3DDF57E704E5
1 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
hw/application_fpga/core/tk1/rtl/tk1.v
View File

@ -75,6 +75,7 @@ module tk1(
localparam ADDR_CDI_FIRST = 8'h20; localparam ADDR_CDI_FIRST = 8'h20;
localparam ADDR_CDI_LAST = 8'h27; localparam ADDR_CDI_LAST = 8'h27;
localparam ADDR_CDI_DONE = 8'h28;
localparam ADDR_UDI_FIRST = 8'h30; localparam ADDR_UDI_FIRST = 8'h30;
localparam ADDR_UDI_LAST = 8'h31; localparam ADDR_UDI_LAST = 8'h31;
@ -144,6 +145,9 @@ module tk1(
reg force_trap_reg; reg force_trap_reg;
reg force_trap_set; reg force_trap_set;
reg cdi_access_reg;
reg cdi_access_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
@ -233,6 +237,7 @@ module tk1(
ram_aslr_reg <= 15'h0; ram_aslr_reg <= 15'h0;
ram_scramble_reg <= 32'h0; ram_scramble_reg <= 32'h0;
force_trap_reg <= 1'h0; force_trap_reg <= 1'h0;
cdi_access_reg <= 1'h1;
end end
else begin else begin
@ -303,6 +308,10 @@ module tk1(
if (force_trap_set) begin if (force_trap_set) begin
force_trap_reg <= 1'h1; force_trap_reg <= 1'h1;
end end
if (cdi_access_we) begin
cdi_access_reg <= 1'h0;
end
end end
end // reg_update end // reg_update
@ -383,7 +392,7 @@ module tk1(
app_size_we = 1'h0; app_size_we = 1'h0;
blake2s_addr_we = 1'h0; blake2s_addr_we = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
cdi_mem_we = 1'h0; cdi_access_we = 1'h0;
ram_aslr_we = 1'h0; ram_aslr_we = 1'h0;
ram_scramble_we = 1'h0; ram_scramble_we = 1'h0;
cpu_mon_en_we = 1'h0; cpu_mon_en_we = 1'h0;
@ -433,6 +442,10 @@ module tk1(
end end
end end
if (address == ADDR_CDI_DONE) begin
cdi_access_we = 1'h1;
end
if (address == ADDR_RAM_ASLR) begin if (address == ADDR_RAM_ASLR) begin
if (!switch_app_reg) begin if (!switch_app_reg) begin
ram_aslr_we = 1'h1; ram_aslr_we = 1'h1;
@ -501,7 +514,9 @@ module tk1(
end end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (cdi_access_reg) begin
tmp_read_data = cdi_mem[address[2 : 0]]; tmp_read_data = cdi_mem[address[2 : 0]];
end
end end
if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin