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Add incoming and outgoing CTS (Clear To Send) signals for the FPGA

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to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
This commit is contained in:
Jonas Thörnblad 2024-12-17 17:18:45 +01:00
parent 5d138ef45b
commit 48cbb55d6e
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GPG key ID: 2D318AD00A326F95
7 changed files with 54 additions and 5 deletions
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4
hw/application_fpga/tb/tb_application_fpga_sim.v
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@ -29,6 +29,8 @@ module tb_application_fpga_sim ();
reg tb_clk = 0;
wire tb_interface_rx;
reg tb_interface_tx = 1'h1; // Set to 1 to simulate inactive UART
reg tb_interface_ch552_cts = 1'h1; // Set to 1 to simulate OK to send
reg tb_interface_fpga_cts;
wire tb_spi_ss;
wire tb_spi_sck;
wire tb_spi_mosi;
@ -49,6 +51,8 @@ module tb_application_fpga_sim ();
.clk(tb_clk),
.interface_rx(tb_interface_rx),
.interface_tx(tb_interface_tx),
.interface_ch552_cts(tb_interface_ch552_cts),
.interface_fpga_cts(tb_interface_fpga_cts),
.spi_ss(tb_spi_ss),
.spi_sck(tb_spi_sck),
.spi_mosi(tb_spi_mosi),