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Add incoming and outgoing CTS (Clear To Send) signals for the FPGA

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to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
This commit is contained in:
Jonas Thörnblad 2024-12-17 17:18:45 +01:00
parent 5d138ef45b
commit 48cbb55d6e
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GPG key ID: 2D318AD00A326F95
7 changed files with 54 additions and 5 deletions
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6
hw/application_fpga/rtl/application_fpga.v
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@ -20,6 +20,9 @@ module application_fpga (
output wire interface_rx,
input wire interface_tx,
input wire interface_ch552_cts, // CH552 clear to send, 1 = OK, 0 = NOK
output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
output wire spi_ss,
output wire spi_sck,
output wire spi_mosi,
@ -293,6 +296,9 @@ module application_fpga (
.rxd(interface_tx),
.txd(interface_rx),
.ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts),
.cs(uart_cs),
.we(uart_we),
.address(uart_address),