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Add incoming and outgoing CTS (Clear To Send) signals for the FPGA

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to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
This commit is contained in:
Jonas Thörnblad 2024-12-17 17:18:45 +01:00
parent 5d138ef45b
commit 48cbb55d6e
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GPG key ID: 2D318AD00A326F95
7 changed files with 54 additions and 5 deletions
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4
hw/application_fpga/data/application_fpga_tk1.pcf
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@ -14,8 +14,8 @@
# UART.
set_io interface_rx 26
set_io interface_tx 25
# set_io interface_cts 27
# set_io interface_rts 28
set_io interface_ch552_cts 27
set_io interface_fpga_cts 28
# SPI master to flash memory.