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https://github.com/tillitis/tillitis-key1.git
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Update application_fpga_sim.v to match application_fpga.v
This commit is contained in:
Jonas Thörnblad
Daniel Jobson
parent
a330aa15ec
commit
4260e1d5ac
@ -23,20 +23,17 @@
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`define verbose(debug_command)
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`endif
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module application_fpga (
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module application_fpga_sim (
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input wire clk,
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output wire valid,
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output wire [03 : 0] wstrb,
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output wire [31 : 0] addr,
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output wire [31 : 0] wdata,
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output wire [31 : 0] rdata,
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output wire ready,
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output wire interface_rx,
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input wire interface_tx,
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output wire spi_ss,
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output wire spi_sck,
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output wire spi_mosi,
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input wire spi_miso,
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input wire touch_event,
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input wire app_gpio1,
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@ -59,14 +56,18 @@ module application_fpga (
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localparam RESERVED_PREFIX = 2'h2;
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localparam MMIO_PREFIX = 2'h3;
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// MMIO core mem sub-prefixes.
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// MMIO core sub-prefixes.
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localparam TRNG_PREFIX = 6'h00;
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localparam TIMER_PREFIX = 6'h01;
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localparam UDS_PREFIX = 6'h02;
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localparam UART_PREFIX = 6'h03;
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localparam TOUCH_SENSE_PREFIX = 6'h04;
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localparam FW_RAM_PREFIX = 6'h10;
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localparam TK1_PREFIX = 6'h3f;
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// Instruction used to cause a trap.
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localparam ILLEGAL_INSTRUCTION = 32'h0;
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//----------------------------------------------------------------
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// Registers, memories with associated wires.
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@ -83,93 +84,84 @@ module application_fpga (
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//----------------------------------------------------------------
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wire reset_n;
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/* verilator lint_off UNOPTFLAT */
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wire cpu_trap;
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wire cpu_valid;
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wire [03 : 0] cpu_wstrb;
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wire cpu_instr;
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wire [ 3 : 0] cpu_wstrb;
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/* verilator lint_off UNUSED */
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wire [31 : 0] cpu_addr;
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wire [31 : 0] cpu_wdata;
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/* verilator lint_off UNOPTFLAT */
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reg rom_cs;
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/* verilator lint_on UNOPTFLAT */
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reg [11 : 0] rom_address;
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wire [31 : 0] rom_read_data;
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wire rom_ready;
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reg ram_cs;
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reg [ 3 : 0] ram_we;
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reg [14 : 0] ram_address;
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reg [15 : 0] ram_address;
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reg [31 : 0] ram_write_data;
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wire [31 : 0] ram_read_data;
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wire ram_ready;
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/* verilator lint_off UNOPTFLAT */
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reg trng_cs;
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/* verilator lint_on UNOPTFLAT */
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reg trng_we;
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reg [ 7 : 0] trng_address;
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reg [31 : 0] trng_write_data;
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wire [31 : 0] trng_read_data;
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wire trng_ready;
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/* verilator lint_off UNOPTFLAT */
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reg timer_cs;
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/* verilator lint_on UNOPTFLAT */
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reg timer_we;
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reg [ 7 : 0] timer_address;
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reg [31 : 0] timer_write_data;
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wire [31 : 0] timer_read_data;
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wire timer_ready;
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/* verilator lint_off UNOPTFLAT */
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reg uds_cs;
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/* verilator lint_on UNOPTFLAT */
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reg [ 7 : 0] uds_address;
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reg [ 2 : 0] uds_address;
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wire [31 : 0] uds_read_data;
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wire uds_ready;
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/* verilator lint_off UNOPTFLAT */
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reg uart_cs;
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/* verilator lint_on UNOPTFLAT */
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reg uart_we;
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reg [ 7 : 0] uart_address;
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reg [31 : 0] uart_write_data;
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wire [31 : 0] uart_read_data;
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wire uart_ready;
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/* verilator lint_off UNOPTFLAT */
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reg fw_ram_cs;
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reg [ 3 : 0] fw_ram_we;
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reg [ 8 : 0] fw_ram_address;
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reg [31 : 0] fw_ram_write_data;
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wire [31 : 0] fw_ram_read_data;
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wire fw_ram_ready;
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reg touch_sense_cs;
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/* verilator lint_on UNOPTFLAT */
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reg touch_sense_we;
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reg [ 7 : 0] touch_sense_address;
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wire [31 : 0] touch_sense_read_data;
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wire touch_sense_ready;
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/* verilator lint_off UNOPTFLAT */
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reg tk1_cs;
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/* verilator lint_on UNOPTFLAT */
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reg tk1_we;
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reg [ 7 : 0] tk1_address;
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reg [31 : 0] tk1_write_data;
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wire [31 : 0] tk1_read_data;
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wire tk1_ready;
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wire system_mode;
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//----------------------------------------------------------------
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// Concurrent assignments.
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//----------------------------------------------------------------
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assign valid = cpu_valid;
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assign wstrb = cpu_wstrb;
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assign addr = cpu_addr;
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assign wdata = cpu_wdata;
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assign rdata = muxed_rdata_reg;
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assign ready = muxed_ready_reg;
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wire force_trap;
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wire [14 : 0] ram_addr_rand;
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wire [31 : 0] ram_data_rand;
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wire tk1_system_reset;
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/* verilator lint_on UNOPTFLAT */
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//----------------------------------------------------------------
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// Module instantiations.
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//----------------------------------------------------------------
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reset_gen #(
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reset_gen_sim #(
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.RESET_CYCLES(200)
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) reset_gen_inst (
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.clk (clk),
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@ -179,35 +171,31 @@ module application_fpga (
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.LATCHED_MEM_RDATA(0),
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.TWO_STAGE_SHIFT(0),
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.TWO_CYCLE_ALU(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0),
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.COMPRESSED_ISA(1),
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.ENABLE_MUL(1),
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.ENABLE_DIV(0),
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.BARREL_SHIFTER(0)
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.CATCH_MISALIGN (0),
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.COMPRESSED_ISA (1),
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.ENABLE_FAST_MUL(1),
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.BARREL_SHIFTER (1)
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) cpu (
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.clk(clk),
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.resetn(reset_n),
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.trap(cpu_trap),
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.mem_valid(cpu_valid),
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.mem_ready(muxed_ready_reg),
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.mem_addr (cpu_addr),
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.mem_wdata(cpu_wdata),
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.mem_wstrb(cpu_wstrb),
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.mem_rdata(muxed_rdata_reg),
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.mem_ready(muxed_ready_reg),
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.mem_instr(cpu_instr),
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// Defined unsed ports. Makes lint happy,
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// but still needs to help lint with empty ports.
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// Defined unused ports. Makes lint happy. But
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// we still needs to help lint with empty ports.
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/* verilator lint_off PINCONNECTEMPTY */
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.irq(32'h0),
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.eoi(),
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.trap(),
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.trace_valid(),
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.trace_data(),
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.mem_instr(),
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.mem_la_read(),
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.mem_la_write(),
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.mem_la_addr(),
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@ -226,6 +214,9 @@ module application_fpga (
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rom rom_inst (
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.clk(clk),
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.reset_n(reset_n),
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.cs(rom_cs),
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.address(rom_address),
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.read_data(rom_read_data),
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@ -237,6 +228,9 @@ module application_fpga (
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.clk(clk),
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.reset_n(reset_n),
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.ram_addr_rand(ram_addr_rand),
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.ram_data_rand(ram_data_rand),
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.cs(ram_cs),
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.we(ram_we),
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.address(ram_address),
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@ -246,6 +240,33 @@ module application_fpga (
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);
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fw_ram fw_ram_inst (
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.clk(clk),
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.reset_n(reset_n),
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.system_mode(system_mode),
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.cs(fw_ram_cs),
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.we(fw_ram_we),
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.address(fw_ram_address),
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.write_data(fw_ram_write_data),
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.read_data(fw_ram_read_data),
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.ready(fw_ram_ready)
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);
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trng_sim trng_inst (
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.clk(clk),
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.reset_n(reset_n),
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.cs(trng_cs),
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.we(trng_we),
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.address(trng_address),
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.write_data(trng_write_data),
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.read_data(trng_read_data),
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.ready(trng_ready)
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);
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timer timer_inst (
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.clk(clk),
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.reset_n(reset_n),
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@ -263,6 +284,8 @@ module application_fpga (
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.clk(clk),
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.reset_n(reset_n),
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.system_mode(system_mode),
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.cs(uds_cs),
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.address(uds_address),
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.read_data(uds_read_data),
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@ -300,12 +323,30 @@ module application_fpga (
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);
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tk1 tk1_inst (
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tk1 #(
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.APP_SIZE(`APP_SIZE)
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) tk1_inst (
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.clk(clk),
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.reset_n(reset_n),
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.system_mode(system_mode),
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.cpu_addr (cpu_addr),
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.cpu_instr (cpu_instr),
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.cpu_valid (cpu_valid),
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.cpu_trap (cpu_trap),
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.force_trap(force_trap),
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.system_reset(tk1_system_reset),
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.ram_addr_rand(ram_addr_rand),
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.ram_data_rand(ram_data_rand),
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.spi_ss (spi_ss),
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.spi_sck (spi_sck),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso),
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.led_r(led_r),
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.led_g(led_g),
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.led_b(led_b),
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@ -330,13 +371,12 @@ module application_fpga (
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//----------------------------------------------------------------
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always @(posedge clk) begin : reg_update
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if (!reset_n) begin
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muxed_ready_reg <= 1'h0;
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muxed_rdata_reg <= 32'h0;
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muxed_ready_reg <= 1'h0;
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end
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else begin
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muxed_ready_reg <= muxed_ready_new;
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muxed_rdata_reg <= muxed_rdata_new;
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muxed_ready_reg <= muxed_ready_new;
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end
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end
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@ -348,7 +388,9 @@ module application_fpga (
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always @* begin : cpu_mem_ctrl
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reg [1 : 0] area_prefix;
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reg [5 : 0] core_prefix;
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reg [255:0] ascii_state;
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ascii_state = "";
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area_prefix = cpu_addr[31 : 30];
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core_prefix = cpu_addr[29 : 24];
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@ -359,10 +401,15 @@ module application_fpga (
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rom_address = cpu_addr[13 : 2];
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ram_cs = 1'h0;
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ram_we = cpu_wstrb;
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ram_address = cpu_addr[16 : 2];
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ram_we = 4'h0;
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ram_address = cpu_addr[17 : 2];
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ram_write_data = cpu_wdata;
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fw_ram_cs = 1'h0;
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fw_ram_we = cpu_wstrb;
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fw_ram_address = cpu_addr[10 : 2];
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fw_ram_write_data = cpu_wdata;
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trng_cs = 1'h0;
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trng_we = |cpu_wstrb;
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trng_address = cpu_addr[9 : 2];
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@ -374,7 +421,7 @@ module application_fpga (
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timer_write_data = cpu_wdata;
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uds_cs = 1'h0;
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uds_address = cpu_addr[9 : 2];
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uds_address = cpu_addr[4 : 2];
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uart_cs = 1'h0;
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uart_we = |cpu_wstrb;
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@ -390,10 +437,21 @@ module application_fpga (
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tk1_address = cpu_addr[9 : 2];
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tk1_write_data = cpu_wdata;
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// Two stage mux implementing read and
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// write access performed based on the address
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// from the CPU.
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if (cpu_valid && !muxed_ready_reg) begin
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if (force_trap) begin
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`verbose($display("Force trap");)
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ascii_state = "Force trap";
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muxed_rdata_new = ILLEGAL_INSTRUCTION;
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muxed_ready_new = 1'h1;
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end
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else begin
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case (area_prefix)
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ROM_PREFIX: begin
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`verbose($display("Access to ROM area");)
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ascii_state = "ROM area";
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rom_cs = 1'h1;
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muxed_rdata_new = rom_read_data;
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muxed_ready_new = rom_ready;
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@ -401,14 +459,17 @@ module application_fpga (
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RAM_PREFIX: begin
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`verbose($display("Access to RAM area");)
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ascii_state = "RAM area";
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ram_cs = 1'h1;
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ram_we = cpu_wstrb;
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muxed_rdata_new = ram_read_data;
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muxed_ready_new = ram_ready;
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end
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RESERVED_PREFIX: begin
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`verbose($display("Access to RESERVED area");)
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muxed_rdata_new = 32'h00000000;
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ascii_state = "RESERVED area";
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muxed_rdata_new = 32'h0;
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muxed_ready_new = 1'h1;
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end
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@ -417,6 +478,7 @@ module application_fpga (
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case (core_prefix)
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TRNG_PREFIX: begin
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`verbose($display("Access to TRNG core");)
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ascii_state = "TRNG core";
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trng_cs = 1'h1;
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muxed_rdata_new = trng_read_data;
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muxed_ready_new = trng_ready;
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@ -424,6 +486,7 @@ module application_fpga (
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TIMER_PREFIX: begin
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`verbose($display("Access to TIMER core");)
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ascii_state = "TIMER core";
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timer_cs = 1'h1;
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muxed_rdata_new = timer_read_data;
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muxed_ready_new = timer_ready;
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@ -431,6 +494,7 @@ module application_fpga (
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UDS_PREFIX: begin
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`verbose($display("Access to UDS core");)
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ascii_state = "UDS core";
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uds_cs = 1'h1;
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muxed_rdata_new = uds_read_data;
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muxed_ready_new = uds_ready;
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@ -438,6 +502,7 @@ module application_fpga (
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UART_PREFIX: begin
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`verbose($display("Access to UART core");)
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ascii_state = "UART core";
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uart_cs = 1'h1;
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muxed_rdata_new = uart_read_data;
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muxed_ready_new = uart_ready;
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@ -445,13 +510,23 @@ module application_fpga (
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TOUCH_SENSE_PREFIX: begin
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`verbose($display("Access to TOUCH_SENSE core");)
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ascii_state = "TOUCH_SENSE core";
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touch_sense_cs = 1'h1;
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muxed_rdata_new = touch_sense_read_data;
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muxed_ready_new = touch_sense_ready;
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end
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FW_RAM_PREFIX: begin
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`verbose($display("Access to FW_RAM core");)
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ascii_state = "FW_RAM core";
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fw_ram_cs = 1'h1;
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muxed_rdata_new = fw_ram_read_data;
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muxed_ready_new = fw_ram_ready;
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end
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TK1_PREFIX: begin
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`verbose($display("Access to TK1 core");)
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ascii_state = "TK1 core";
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tk1_cs = 1'h1;
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muxed_rdata_new = tk1_read_data;
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muxed_ready_new = tk1_ready;
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@ -459,7 +534,8 @@ module application_fpga (
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default: begin
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`verbose($display("UNDEFINED MMIO");)
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muxed_rdata_new = 32'h00000000;
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ascii_state = "UNDEFINED MMIO";
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muxed_rdata_new = 32'h0;
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muxed_ready_new = 1'h1;
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end
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endcase // case (core_prefix)
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@ -467,15 +543,17 @@ module application_fpga (
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default: begin
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`verbose($display("UNDEFINED AREA");)
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ascii_state = "UNDEFINED AREA";
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muxed_rdata_new = 32'h0;
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muxed_ready_new = 1'h1;
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end
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endcase // case (area_prefix)
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end
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end // if (force_trap) begin end else begin
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end // if (cpu_valid && !muxed_ready_reg) begin
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end
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endmodule // application_fpga
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//======================================================================
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// EOF application_fpga.v
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// EOF application_fpga_sim.v
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//======================================================================
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