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Make synth.json depend on data/{uds,udi}.hex; revise docs

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Daniel Lublin 2022-09-20 16:34:58 +02:00
parent 6ff117cb5d
commit 40803993e1
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3 changed files with 22 additions and 13 deletions
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25
doc/quickstart.md
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@ -13,6 +13,8 @@ The Tillitis Key1 kit includes:
- USB-C cable
- USB-C to USB-A adapter
# Programming FPGA bitstream and firmware onto Tillitis Key 1
Connect the programmer to the computer using the mentioned cable. It
is convenient to connect the USB device to the USB-C cable, and then
connect the cable to the computer. The latter using the USB-C-to-A, if
@ -40,15 +42,22 @@ $ cd tillitis-key1/hw/application_fpga
$ make prog_flash
```
After programming, when your Key1 device is connected to the host, it would boot the firmware.
When boot has completed, the device will start flashing the LED white. This indicates that the device
is ready to receive and measure an app.
After programming, when your device is connected to the host, it would boot the
firmware. When boot has completed, the device will start flashing the LED
white. This indicates that the device is ready to receive and measure an app.
To personalize the device, you need to modify the hex file that contain the Unique Device Secret (UDS).
You should also update the Unique Device Identity (UDI). These hex files are located in hw/application_fpga/data.
To make this easier there is a tool, tpt that can generate these files. The tool can be found in hw/application_fpga/tools/tpt.
The tool allow you to supply a secret used as part of the UDS generation. The tool can be run interactively, or by suppling
inputs on the command line:
# Device personalization
To personalize the device, you need to modify the hex file that contains the
Unique Device Secret (UDS). You should also update the Unique Device Identity
(UDI). These hex files are located in `hw/application_fpga/data/`. Note that
after modify the files in this directory, you need to rebuild and program the
device again (as above).
To make this easier there is a tool that can generate these files. The tool can
be found in `hw/application_fpga/tools/tpt`. The tool allow you to supply a
secret used as part of the UDS generation. The tool can be run interactively,
or by suppling inputs on the command line:
```
usage: tpt.py [-h] [-v] [--uss USS] [--vid VID] [--pid PID] [--rev REV] [--serial SERIAL]

2
hw/application_fpga/Makefile
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@ -168,7 +168,7 @@ verilator: $(VERILATOR_TOP_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
# Main FPGA build flow.
# Synthesis. Place & Route. Bitstream generation.
#-------------------------------------------------------------------
synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex
synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \