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Make synth.json depend on data/{uds,udi}.hex; revise docs

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Daniel Lublin 2022-09-20 16:34:58 +02:00
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2
README.md
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@ -32,7 +32,7 @@ The first implementation is the Tillitis Key 1:
* [Boards](hw/boards/README.md) * [Boards](hw/boards/README.md)
* [Firmware](hw/application_fpga/fw/mta1_mkdf/README.md) * [Firmware](hw/application_fpga/fw/mta1_mkdf/README.md)
* [Toolchain setup](doc/toolchain_setup.md) * [Toolchain setup](doc/toolchain_setup.md)
* [Quickstart](doc/quickstart.md) to program the Tillitis Key1 * [Quickstart](doc/quickstart.md) to program the Tillitis Key 1
* [Release Notes](doc/release_notes.md) * [Release Notes](doc/release_notes.md)
## About this repository ## About this repository

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doc/quickstart.md
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@ -1,11 +1,11 @@
This document describes how to build the FPGA bitstream, including the This document describes how to build the FPGA bitstream, including the
firmware, and get this programmed onto the flash of the Tillitis Key1 firmware, and get this programmed onto the flash of the Tillitis Key 1
USB device. USB device.
The Tillitis Key1 kit includes: The Tillitis Key 1 kit includes:
- Tillitis Key1 USB device, marked MTA1-USB V1 - Tillitis Key 1 USB device, marked MTA1-USB V1
- Programmer board based on Raspberry Pi Pico, with a white device - Programmer board based on Raspberry Pi Pico, with a white device
holder/jig holder/jig
- USB-cable with micro-B plug, for connecting the programmer to - USB-cable with micro-B plug, for connecting the programmer to
@ -13,6 +13,8 @@ The Tillitis Key1 kit includes:
- USB-C cable - USB-C cable
- USB-C to USB-A adapter - USB-C to USB-A adapter
# Programming FPGA bitstream and firmware onto Tillitis Key 1
Connect the programmer to the computer using the mentioned cable. It Connect the programmer to the computer using the mentioned cable. It
is convenient to connect the USB device to the USB-C cable, and then is convenient to connect the USB device to the USB-C cable, and then
connect the cable to the computer. The latter using the USB-C-to-A, if connect the cable to the computer. The latter using the USB-C-to-A, if
@ -40,15 +42,22 @@ $ cd tillitis-key1/hw/application_fpga
$ make prog_flash $ make prog_flash
``` ```
After programming, when your Key1 device is connected to the host, it would boot the firmware. After programming, when your device is connected to the host, it would boot the
When boot has completed, the device will start flashing the LED white. This indicates that the device firmware. When boot has completed, the device will start flashing the LED
is ready to receive and measure an app. white. This indicates that the device is ready to receive and measure an app.
To personalize the device, you need to modify the hex file that contain the Unique Device Secret (UDS). # Device personalization
You should also update the Unique Device Identity (UDI). These hex files are located in hw/application_fpga/data.
To make this easier there is a tool, tpt that can generate these files. The tool can be found in hw/application_fpga/tools/tpt. To personalize the device, you need to modify the hex file that contains the
The tool allow you to supply a secret used as part of the UDS generation. The tool can be run interactively, or by suppling Unique Device Secret (UDS). You should also update the Unique Device Identity
inputs on the command line: (UDI). These hex files are located in `hw/application_fpga/data/`. Note that
after modify the files in this directory, you need to rebuild and program the
device again (as above).
To make this easier there is a tool that can generate these files. The tool can
be found in `hw/application_fpga/tools/tpt`. The tool allow you to supply a
secret used as part of the UDS generation. The tool can be run interactively,
or by suppling inputs on the command line:
``` ```
usage: tpt.py [-h] [-v] [--uss USS] [--vid VID] [--pid PID] [--rev REV] [--serial SERIAL] usage: tpt.py [-h] [-v] [--uss USS] [--vid VID] [--pid PID] [--rev REV] [--serial SERIAL]

2
hw/application_fpga/Makefile
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@ -168,7 +168,7 @@ verilator: $(VERILATOR_TOP_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
# Main FPGA build flow. # Main FPGA build flow.
# Synthesis. Place & Route. Bitstream generation. # Synthesis. Place & Route. Bitstream generation.
#------------------------------------------------------------------- #-------------------------------------------------------------------
synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ $(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \ -DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \ -DUDS_HEX=\"$(P)/data/uds.hex\" \