Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-12-15 16:49:15 -05:00
Code Issues Projects Releases Packages Wiki Activity

Make synth.json depend on data/{uds,udi}.hex; revise docs

Browse source
This commit is contained in:
Daniel Lublin 2022-09-20 16:34:58 +02:00
parent 6ff117cb5d
commit 40803993e1
No known key found for this signature in database
GPG key ID: 75BD0FEB8D3E7830
3 changed files with 22 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/application_fpga/Makefile
View file

@ -168,7 +168,7 @@ verilator: $(VERILATOR_TOP_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
# Main FPGA build flow.
# Synthesis. Place & Route. Bitstream generation.
#-------------------------------------------------------------------
synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex
synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \