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Add API address to read out number of bytes in Rx FIFO

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-01-03 09:56:33 +01:00
parent 4db4e39205
commit 3eb5b7879c
4 changed files with 16 additions and 3 deletions
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8
hw/application_fpga/core/uart/rtl/uart.v
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@ -75,6 +75,7 @@ module uart(
localparam ADDR_RX_STATUS = 8'h20;
localparam ADDR_RX_DATA = 8'h21;
localparam ADDR_RX_BYTES = 8'h22;
localparam ADDR_TX_STATUS = 8'h40;
localparam ADDR_TX_DATA = 8'h41;
@ -117,6 +118,7 @@ module uart(
wire fifo_out_syn;
wire [7 : 0] fifo_out_data;
reg fifo_out_ack;
wire [8 : 0] fifo_bytes;
reg [31 : 0] tmp_read_data;
reg tmp_ready;
@ -165,6 +167,8 @@ module uart(
.in_data(core_rxd_data),
.in_ack(core_rxd_ack),
.fifo_bytes(fifo_bytes),
.out_syn(fifo_out_syn),
.out_data(fifo_out_data),
.out_ack(fifo_out_ack)
@ -271,6 +275,10 @@ module uart(
tmp_read_data = {24'h0, fifo_out_data};
end
ADDR_RX_BYTES: begin
tmp_read_data = {23'h0, fifo_bytes};
end
ADDR_TX_STATUS: begin
tmp_read_data = {31'h0, core_txd_ready};
end

9
hw/application_fpga/core/uart/rtl/uart_fifo.v
View file

@ -44,6 +44,8 @@ module uart_fifo(
input wire [7 : 0] in_data,
output wire in_ack,
output wire [8 : 0] fifo_bytes,
output wire out_syn,
output wire [7 : 0] out_data,
input wire out_ack
@ -84,9 +86,10 @@ module uart_fifo(
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign in_ack = in_ack_reg;
assign out_syn = ~fifo_empty;
assign out_data = fifo_mem[out_ptr_reg];
assign in_ack = in_ack_reg;
assign out_syn = ~fifo_empty;
assign out_data = fifo_mem[out_ptr_reg];
assign fifo_bytes = byte_ctr_reg;
//----------------------------------------------------------------