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https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
FPGA: Move sample point to not miss MISO lsb
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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parent
53c5e70795
commit
3d8491af71
@ -229,7 +229,6 @@ module tk1_spi_master(
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spi_ctrl_new = CTRL_IDLE;
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spi_ctrl_we = 1'h0;
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case (spi_ctrl_reg)
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CTRL_IDLE: begin
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if (spi_start) begin
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@ -244,14 +243,14 @@ module tk1_spi_master(
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end
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CTRL_POS_FLANK: begin
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spi_rx_data_nxt = 1'h1;
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spi_csk_new = 1'h1;
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spi_csk_we = 1'h1;
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spi_ctrl_new = CTRL_NEG_FLANK;
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spi_ctrl_we = 1'h1;
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spi_ctrl_new = CTRL_NEG_FLANK;
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spi_ctrl_we = 1'h1;
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end
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CTRL_NEG_FLANK: begin
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spi_tx_data_nxt = 1'h1;
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spi_csk_new = 1'h0;
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spi_csk_we = 1'h1;
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spi_ctrl_new = CTRL_NEXT;
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@ -259,6 +258,7 @@ module tk1_spi_master(
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end
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CTRL_NEXT: begin
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spi_rx_data_nxt = 1'h1;
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if (spi_bit_ctr_reg == 3'h7) begin
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spi_ready_new = 1'h1;
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spi_ready_we = 1'h1;
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@ -266,7 +266,6 @@ module tk1_spi_master(
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spi_ctrl_we = 1'h1;
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end
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else begin
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spi_tx_data_nxt = 1'h1;
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spi_bit_ctr_inc = 1'h1;
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spi_ctrl_new = CTRL_POS_FLANK;
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spi_ctrl_we = 1'h1;
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