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FPGA: Format verilog code

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This commit is contained in:
Jonas Thörnblad 2024-10-22 11:54:56 +02:00 committed by Daniel Jobson
parent e04aacda48
commit 3514d7ef3c
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GPG Key ID: 3707A9DBF4BB8F1A
30 changed files with 3477 additions and 3579 deletions
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29
hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
View File

@ -16,13 +16,14 @@
`default_nettype none
module clk_reset_gen #(parameter RESET_CYCLES = 200)
(
module clk_reset_gen #(
parameter RESET_CYCLES = 200
) (
input wire sys_reset,
output wire clk,
output wire rst_n
);
);
//----------------------------------------------------------------
@ -58,8 +59,13 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
// Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
SB_HFOSC #(.CLKHF_DIV("0b10")
) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
SB_HFOSC #(
.CLKHF_DIV("0b10")
) hfosc_inst (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (hfosc_clk)
);
// Use a PLL to generate a new clock frequency based on the HFOSC clock.
@ -89,8 +95,8 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
// Use a Global Buffer to distribute the clock.
SB_GB gb_inst (
.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
.GLOBAL_BUFFER_OUTPUT (clk)
.USER_SIGNAL_TO_GLOBAL_BUFFER(pll_clk),
.GLOBAL_BUFFER_OUTPUT(clk)
);
/* verilator lint_on PINMISSING */
@ -99,21 +105,18 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//----------------------------------------------------------------
// reg_update.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset;
if (rst_ctr_we)
rst_ctr_reg <= rst_ctr_new;
if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
end
//----------------------------------------------------------------
// rst_logic.
//----------------------------------------------------------------
always @*
begin : rst_logic
always @* begin : rst_logic
rst_n_new = 1'h1;
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;

22
hw/application_fpga/core/fw_ram/rtl/fw_ram.v
View File

@ -13,19 +13,19 @@
`default_nettype none
module fw_ram(
module fw_ram (
input wire clk,
input wire reset_n,
input wire fw_app_mode,
input wire cs,
input wire [3 : 0] we,
input wire [8 : 0] address,
input wire [ 3 : 0] we,
input wire [ 8 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -51,7 +51,7 @@ module fw_ram(
//----------------------------------------------------------------
// Block RAM instances.
//----------------------------------------------------------------
SB_RAM40_4K fw_ram0_0(
SB_RAM40_4K fw_ram0_0 (
.RDATA(mem_read_data0[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
@ -65,7 +65,7 @@ module fw_ram(
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
SB_RAM40_4K fw_ram0_1(
SB_RAM40_4K fw_ram0_1 (
.RDATA(mem_read_data0[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
@ -80,7 +80,7 @@ module fw_ram(
);
SB_RAM40_4K fw_ram1_0(
SB_RAM40_4K fw_ram1_0 (
.RDATA(mem_read_data1[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
@ -94,7 +94,7 @@ module fw_ram(
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
SB_RAM40_4K fw_ram1_1(
SB_RAM40_4K fw_ram1_1 (
.RDATA(mem_read_data1[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
@ -111,8 +111,7 @@ module fw_ram(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
ready_reg <= 1'h0;
end
@ -125,8 +124,7 @@ module fw_ram(
//----------------------------------------------------------------
// rw_mux
//----------------------------------------------------------------
always @*
begin : rw_mux;
always @* begin : rw_mux
bank0 = 1'h0;
bank1 = 1'h0;
tmp_read_data = 32'h0;

26
hw/application_fpga/core/ram/rtl/ram.v
View File

@ -18,7 +18,7 @@
`default_nettype none
module ram(
module ram (
input wire clk,
input wire reset_n,
@ -26,12 +26,12 @@ module ram(
input wire [31 : 0] ram_data_rand,
input wire cs,
input wire [03 : 0] we,
input wire [ 3 : 0] we,
input wire [15 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -60,7 +60,7 @@ module ram(
//----------------------------------------------------------------
// SPRAM instances.
//----------------------------------------------------------------
SB_SPRAM256KA spram0(
SB_SPRAM256KA spram0 (
.ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[15:0]),
.MASKWREN({we[1], we[1], we[0], we[0]}),
@ -73,7 +73,7 @@ module ram(
.DATAOUT(read_data0[15:0])
);
SB_SPRAM256KA spram1(
SB_SPRAM256KA spram1 (
.ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[31:16]),
.MASKWREN({we[3], we[3], we[2], we[2]}),
@ -87,7 +87,7 @@ module ram(
);
SB_SPRAM256KA spram2(
SB_SPRAM256KA spram2 (
.ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[15:0]),
.MASKWREN({we[1], we[1], we[0], we[0]}),
@ -100,7 +100,7 @@ module ram(
.DATAOUT(read_data1[15:0])
);
SB_SPRAM256KA spram3(
SB_SPRAM256KA spram3 (
.ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[31:16]),
.MASKWREN({we[3], we[3], we[2], we[2]}),
@ -121,8 +121,7 @@ module ram(
// This simply creates a one cycle access latency to match
// the latency of the spram blocks.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
ready_reg <= 1'h0;
end
@ -138,8 +137,7 @@ module ram(
// Scramble address and write data, and descramble read data using
// the ram_addr_rand and ram_data_rand seeds.
//----------------------------------------------------------------
always @*
begin: scramble_descramble
always @* begin : scramble_descramble
scrambled_ram_addr = address[14 : 0] ^ ram_addr_rand;
scrambled_write_data = write_data ^ ram_data_rand ^ {2{address}};
descrambled_read_data = muxed_read_data ^ ram_data_rand ^ {2{address}};
@ -152,14 +150,14 @@ module ram(
// Select which of the data read from the banks should be
// returned during a read access.
//----------------------------------------------------------------
always @*
begin : mem_mux
always @* begin : mem_mux
cs0 = ~scrambled_ram_addr[14] & cs;
cs1 = scrambled_ram_addr[14] & cs;
if (scrambled_ram_addr[14]) begin
muxed_read_data = read_data1;
end else begin
end
else begin
muxed_read_data = read_data0;
end
end

12
hw/application_fpga/core/rom/rtl/rom.v
View File

@ -14,7 +14,7 @@
`default_nettype none
module rom(
module rom (
input wire clk,
input wire reset_n,
@ -24,7 +24,7 @@ module rom(
/* verilator lint_on UNUSED */
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -41,7 +41,7 @@ module rom(
// Max size for the ROM is 3072 words, and the address is
// 12 bits to support ROM with this number of words.
localparam EBR_MEM_SIZE = `BRAM_FW_SIZE;
reg [31 : 0] memory [0 : (EBR_MEM_SIZE - 1)];
reg [31 : 0] memory[0 : (EBR_MEM_SIZE - 1)];
initial $readmemh(`FIRMWARE_HEX, memory);
reg [31 : 0] rom_rdata;
@ -58,8 +58,7 @@ module rom(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
ready_reg <= 1'h0;
end
@ -72,8 +71,7 @@ module rom(
//----------------------------------------------------------------
// rom_logic
//----------------------------------------------------------------
always @*
begin : rom_logic
always @* begin : rom_logic
/* verilator lint_off WIDTH */
rom_rdata = memory[address];
/* verilator lint_on WIDTH */

14
hw/application_fpga/core/timer/rtl/timer.v
View File

@ -13,18 +13,18 @@
`default_nettype none
module timer(
module timer (
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -77,7 +77,7 @@ module timer(
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
timer_core core(
timer_core core (
.clk(clk),
.reset_n(reset_n),
@ -94,8 +94,7 @@ module timer(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
start_reg <= 1'h0;
stop_reg <= 1'h0;
@ -122,8 +121,7 @@ module timer(
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
always @* begin : api
start_new = 1'h0;
stop_new = 1'h0;
prescaler_we = 1'h0;

26
hw/application_fpga/core/timer/rtl/timer_core.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module timer_core(
module timer_core (
input wire clk,
input wire reset_n,
@ -24,7 +24,7 @@ module timer_core(
output wire [31 : 0] curr_timer,
output wire running
);
);
//----------------------------------------------------------------
@ -54,8 +54,8 @@ module timer_core(
reg timer_set;
reg timer_dec;
reg [1 : 0] core_ctrl_reg;
reg [1 : 0] core_ctrl_new;
reg [ 1 : 0] core_ctrl_reg;
reg [ 1 : 0] core_ctrl_new;
reg core_ctrl_we;
@ -69,17 +69,14 @@ module timer_core(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin: reg_update
if (!reset_n)
begin
always @(posedge clk) begin : reg_update
if (!reset_n) begin
running_reg <= 1'h0;
prescaler_reg <= 32'h0;
timer_reg <= 32'h0;
core_ctrl_reg <= CTRL_IDLE;
end
else
begin
else begin
if (running_we) begin
running_reg <= running_new;
end
@ -102,8 +99,7 @@ module timer_core(
//----------------------------------------------------------------
// prescaler_ctr
//----------------------------------------------------------------
always @*
begin : prescaler_ctr
always @* begin : prescaler_ctr
prescaler_new = 32'h0;
prescaler_we = 1'h0;
@ -121,8 +117,7 @@ module timer_core(
//----------------------------------------------------------------
// timer_ctr
//----------------------------------------------------------------
always @*
begin : timer_ctr
always @* begin : timer_ctr
timer_new = 32'h0;
timer_we = 1'h0;
@ -140,8 +135,7 @@ module timer_core(
//----------------------------------------------------------------
// Core control FSM.
//----------------------------------------------------------------
always @*
begin : core_ctrl
always @* begin : core_ctrl
running_new = 1'h0;
running_we = 1'h0;
prescaler_set = 1'h0;

42
hw/application_fpga/core/timer/tb/tb_timer.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tb_timer();
module tb_timer ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -47,7 +47,7 @@ module tb_timer();
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_ready;
@ -58,7 +58,7 @@ module tb_timer();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
timer dut(
timer dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
@ -77,8 +77,7 @@ module tb_timer();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -90,12 +89,10 @@ module tb_timer();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
if (tb_monitor) begin
dump_dut_state();
end
end
@ -113,13 +110,15 @@ module tb_timer();
$display("Cycle: %08d", cycle_ctr);
$display("");
$display("Inputs and outputs:");
$display("cs: 0x%1x, we: 0x%1x, address: 0x%02x, write_data: 0x%08x, read_data: 0x%08x, ready: 0x%1x",
$display(
"cs: 0x%1x, we: 0x%1x, address: 0x%02x, write_data: 0x%08x, read_data: 0x%08x, ready: 0x%1x",
tb_cs, tb_we, tb_address, tb_write_data, tb_read_data, tb_ready);
$display("");
$display("Internal state:");
$display("prescaler_reg: 0x%08x, timer_reg: 0x%08x", dut.prescaler_reg, dut.timer_reg);
$display("start_reg: 0x%1x, stop_reg: 0x%1x", dut.start_reg, dut.stop_reg);
$display("core_running: 0x%1x, core_curr_timer: 0x%08x", dut.core_running, dut.core_curr_timer);
$display("core_running: 0x%1x, core_curr_timer: 0x%08x", dut.core_running,
dut.core_curr_timer);
$display("");
$display("");
end
@ -148,12 +147,10 @@ module tb_timer();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
@ -189,11 +186,9 @@ module tb_timer();
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
task write_word(input [11 : 0] address, input [31 : 0] word);
begin
if (DEBUG) begin
$display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
@ -225,8 +220,7 @@ module tb_timer();
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
if (DEBUG) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
@ -242,8 +236,7 @@ module tb_timer();
task wait_ready;
begin : wready
read_word(ADDR_STATUS);
while (read_data == 0)
read_word(ADDR_STATUS);
while (read_data == 0) read_word(ADDR_STATUS);
end
endtask // wait_ready
@ -292,8 +285,7 @@ module tb_timer();
//----------------------------------------------------------------
// timer_test
//----------------------------------------------------------------
initial
begin : timer_test
initial begin : timer_test
$display("");
$display(" -= Testbench for timer started =-");
$display(" =============================");

41
hw/application_fpga/core/timer/tb/tb_timer_core.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tb_timer_core();
module tb_timer_core ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -46,7 +46,7 @@ module tb_timer_core();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
timer_core dut(
timer_core dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
.prescaler_init(tb_prescaler_init),
@ -63,8 +63,7 @@ module tb_timer_core();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -76,12 +75,10 @@ module tb_timer_core();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
if (tb_monitor) begin
dump_dut_state();
end
end
@ -99,21 +96,16 @@ module tb_timer_core();
$display("Cycle: %08d", cycle_ctr);
$display("");
$display("Inputs and outputs:");
$display("prescaler_init: 0x%08x, timer_init: 0x%08x",
dut.prescaler_init, dut.timer_init);
$display("start: 0x%1x, stop: 0x%1x, running: 0x%1x",
dut.start, dut.stop, dut.running);
$display("prescaler_init: 0x%08x, timer_init: 0x%08x", dut.prescaler_init, dut.timer_init);
$display("start: 0x%1x, stop: 0x%1x, running: 0x%1x", dut.start, dut.stop, dut.running);
$display("");
$display("Internal state:");
$display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x",
dut.prescaler_reg, dut.prescaler_new);
$display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x",
dut.prescaler_set, dut.prescaler_dec);
$display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x", dut.prescaler_reg,
dut.prescaler_new);
$display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x", dut.prescaler_set, dut.prescaler_dec);
$display("");
$display("timer_reg: 0x%08x, timer_new: 0x%08x",
dut.timer_reg, dut.timer_new);
$display("timer_set: 0x%1x, timer_dec: 0x%1x",
dut.timer_set, dut.timer_dec);
$display("timer_reg: 0x%08x, timer_new: 0x%08x", dut.timer_reg, dut.timer_new);
$display("timer_set: 0x%1x, timer_dec: 0x%1x", dut.timer_set, dut.timer_dec);
$display("");
$display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x",
dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
@ -154,11 +146,9 @@ module tb_timer_core();
task wait_done;
begin
#(2 * CLK_PERIOD);
while (tb_running)
begin
while (tb_running) begin
#(CLK_PERIOD);
if (DUMP_WAIT)
begin
if (DUMP_WAIT) begin
dump_dut_state();
end
end
@ -220,8 +210,7 @@ module tb_timer_core();
//
// Test vectors from:
//----------------------------------------------------------------
initial
begin : timer_core_test
initial begin : timer_core_test
$display("--- Simulation of timer core started.");
$display("");

56
hw/application_fpga/core/tk1/rtl/tk1.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tk1(
module tk1 (
input wire clk,
input wire reset_n,
@ -45,11 +45,11 @@ module tk1(
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -115,11 +115,11 @@ module tk1(
reg switch_app_reg;
reg switch_app_we;
reg [2 : 0] led_reg;
reg [ 2 : 0] led_reg;
reg led_we;
reg [1 : 0] gpio1_reg;
reg [1 : 0] gpio2_reg;
reg [ 1 : 0] gpio1_reg;
reg [ 1 : 0] gpio2_reg;
reg gpio3_reg;
reg gpio3_we;
reg gpio4_reg;
@ -136,8 +136,8 @@ module tk1(
reg [23 : 0] cpu_trap_ctr_reg;
reg [23 : 0] cpu_trap_ctr_new;
reg [2 : 0] cpu_trap_led_reg;
reg [2 : 0] cpu_trap_led_new;
reg [ 2 : 0] cpu_trap_led_reg;
reg [ 2 : 0] cpu_trap_led_new;
reg cpu_trap_led_we;
reg [14 : 0] ram_addr_rand_reg;
@ -167,17 +167,17 @@ module tk1(
reg tmp_ready;
/* verilator lint_on UNOPTFLAT */
reg [2 : 0] muxed_led;
reg [ 2 : 0] muxed_led;
wire [31:0] udi_rdata;
wire [31 : 0] udi_rdata;
reg spi_enable;
reg spi_enable_vld;
reg spi_start;
reg [7 : 0] spi_tx_data;
reg [ 7 : 0] spi_tx_data;
reg spi_tx_data_vld;
wire spi_ready;
wire [7 : 0] spi_rx_data;
wire [ 7 : 0] spi_rx_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
@ -219,12 +219,12 @@ module tk1(
);
/* verilator lint_on PINMISSING */
tk1_spi_master spi_master(
tk1_spi_master spi_master (
.clk(clk),
.reset_n(reset_n),
.spi_ss(spi_ss),
.spi_sck(spi_sck),
.spi_ss (spi_ss),
.spi_sck (spi_sck),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
@ -237,7 +237,7 @@ module tk1(
.spi_ready(spi_ready)
);
udi_rom rom_i(
udi_rom rom_i (
.addr(address[0]),
.data(udi_rdata)
);
@ -246,8 +246,7 @@ module tk1(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
switch_app_reg <= 1'h0;
led_reg <= 3'h6;
@ -354,8 +353,7 @@ module tk1(
//----------------------------------------------------------------
// trap_led_logic
//----------------------------------------------------------------
always @*
begin : trap_led_logic
always @* begin : trap_led_logic
cpu_trap_led_new = 3'h0;
cpu_trap_led_we = 1'h0;
@ -368,7 +366,8 @@ module tk1(
if (cpu_trap) begin
muxed_led = cpu_trap_led_reg;
end else begin
end
else begin
muxed_led = led_reg;
end
end
@ -388,8 +387,7 @@ module tk1(
// This requires execution monitor to have been setup and
// enabled.
//----------------------------------------------------------------
always @*
begin : security_monitor
always @* begin : security_monitor
force_trap_set = 1'h0;
if (cpu_valid) begin
@ -398,14 +396,12 @@ module tk1(
end
if (cpu_instr) begin
if ((cpu_addr >= FW_RAM_FIRST) &&
(cpu_addr <= FW_RAM_LAST)) begin
if ((cpu_addr >= FW_RAM_FIRST) && (cpu_addr <= FW_RAM_LAST)) begin
force_trap_set = 1'h1;
end
if (cpu_mon_en_reg) begin
if ((cpu_addr >= cpu_mon_first_reg) &&
(cpu_addr <= cpu_mon_last_reg)) begin
if ((cpu_addr >= cpu_mon_first_reg) && (cpu_addr <= cpu_mon_last_reg)) begin
force_trap_set = 1'h1;
end
end
@ -417,8 +413,7 @@ module tk1(
//----------------------------------------------------------------
// api
//----------------------------------------------------------------
always @*
begin : api
always @* begin : api
switch_app_we = 1'h0;
led_we = 1'h0;
gpio3_we = 1'h0;
@ -552,8 +547,7 @@ module tk1(
end
if (address == ADDR_GPIO) begin
tmp_read_data = {28'h0, gpio4_reg, gpio3_reg,
gpio2_reg[1], gpio1_reg[1]};
tmp_read_data = {28'h0, gpio4_reg, gpio3_reg, gpio2_reg[1], gpio1_reg[1]};
end
if (address == ADDR_APP_START) begin

19
hw/application_fpga/core/tk1/rtl/tk1_spi_master.v
View File

@ -23,7 +23,7 @@
`default_nettype none
module tk1_spi_master(
module tk1_spi_master (
input wire clk,
input wire reset_n,
@ -39,7 +39,7 @@ module tk1_spi_master(
input wire spi_tx_data_vld,
output wire [7 : 0] spi_rx_data,
output wire spi_ready
);
);
//----------------------------------------------------------------
@ -100,8 +100,7 @@ module tk1_spi_master(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
spi_ss_reg <= 1'h1;
spi_csk_reg <= 1'h0;
@ -150,8 +149,7 @@ module tk1_spi_master(
//----------------------------------------------------------------
// bit_ctr
//----------------------------------------------------------------
always @*
begin : bit_ctr
always @* begin : bit_ctr
spi_bit_ctr_new = 3'h0;
spi_bit_ctr_we = 1'h0;
@ -173,8 +171,7 @@ module tk1_spi_master(
// Logic for the tx_data shift register.
// Either load or shift the data register.
//----------------------------------------------------------------
always @*
begin : spi_tx_data_logic
always @* begin : spi_tx_data_logic
spi_tx_data_new = 8'h0;
spi_tx_data_we = 1'h0;
@ -196,8 +193,7 @@ module tk1_spi_master(
// spi_rx_data_logic
// Logic for the rx_data shift register.
//----------------------------------------------------------------
always @*
begin : spi_rx_data_logic
always @* begin : spi_rx_data_logic
spi_rx_data_new = 8'h0;
spi_rx_data_we = 1'h0;
@ -216,8 +212,7 @@ module tk1_spi_master(
//----------------------------------------------------------------
// spi_master_ctrl
//----------------------------------------------------------------
always @*
begin : spi_master_ctrl
always @* begin : spi_master_ctrl
spi_rx_data_nxt = 1'h0;
spi_tx_data_nxt = 1'h0;
spi_csk_new = 1'h0;

10
hw/application_fpga/core/tk1/rtl/udi_rom.v
View File

@ -13,19 +13,19 @@
//======================================================================
module udi_rom (
input wire [0:0] addr,
input wire [ 0:0] addr,
output wire [31:0] data
);
generate
genvar ii;
/* verilator lint_off PINMISSING */
for (ii = 0; ii < 32; ii = ii + 1'b1)
begin: luts
for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts
(* udi_rom_idx=ii, keep *) SB_LUT4 #(.LUT_INIT({2'h1})
(* udi_rom_idx=ii, keep *) SB_LUT4 #(
.LUT_INIT({2'h1})
) lut_i (
.I0(addr[0]),
.O(data[ii])
.O (data[ii])
);
/* verilator lint_on PINMISSING */
end

2
hw/application_fpga/core/tk1/tb/sb_rgba_drv.v
View File

@ -28,7 +28,7 @@ module SB_RGBA_DRV (
output wire RGB0,
output wire RGB1,
output wire RGB2
);
);
/* verilator lint_off UNUSEDPARAM */
parameter CURRENT_MODE = 1;

76
hw/application_fpga/core/tk1/tb/tb_tk1.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tb_tk1();
module tb_tk1 ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -102,7 +102,7 @@ module tb_tk1();
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_ready;
@ -117,16 +117,16 @@ module tb_tk1();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
tk1 dut(
tk1 dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
.cpu_trap(tb_cpu_trap),
.fw_app_mode(tb_fw_app_mode),
.cpu_addr(tb_cpu_addr),
.cpu_instr(tb_cpu_instr),
.cpu_valid(tb_cpu_valid),
.cpu_addr (tb_cpu_addr),
.cpu_instr (tb_cpu_instr),
.cpu_valid (tb_cpu_valid),
.force_trap(tb_force_trap),
.ram_addr_rand(tb_ram_addr_rand),
@ -141,8 +141,8 @@ module tb_tk1();
.gpio3(tb_gpio3),
.gpio4(tb_gpio4),
.spi_ss(tb_spi_ss),
.spi_sck(tb_spi_sck),
.spi_ss (tb_spi_ss),
.spi_sck (tb_spi_sck),
.spi_mosi(tb_spi_mosi),
.spi_miso(tb_spi_miso),
@ -160,8 +160,7 @@ module tb_tk1();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -173,12 +172,10 @@ module tb_tk1();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
if (tb_monitor) begin
dump_dut_state();
end
end
@ -198,9 +195,11 @@ module tb_tk1();
$display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode);
$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand, tb_ram_data_rand);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand,
tb_ram_data_rand);
$display("led_r: 0x%1x, led_g: 0x%1x, led_b: 0x%1x", tb_led_r, tb_led_g, tb_led_b);
$display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we, tb_address);
$display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we,
tb_address);
$display("write_data: 0x%08x, read_data: 0x%08x", tb_write_data, tb_read_data);
$display("");
@ -211,8 +210,8 @@ module tb_tk1();
if (tb_spi_monitor) begin
$display("SPI I/O and internal state:");
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso: 0x%1x",
tb_spi_ss, tb_spi_sck, tb_spi_mosi, tb_spi_miso);
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso: 0x%1x", tb_spi_ss,
tb_spi_sck, tb_spi_mosi, tb_spi_miso);
end
$display("");
@ -243,12 +242,10 @@ module tb_tk1();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("--- %02d tests completed - %02d errors detected.", tc_ctr, error_ctr);
end
end
@ -293,11 +290,9 @@ module tb_tk1();
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
task write_word(input [11 : 0] address, input [31 : 0] word);
begin
if (DEBUG) begin
$display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
@ -359,13 +354,13 @@ module tb_tk1();
#(CLK_PERIOD);
tb_cs = 1'h0;
if (DEBUG)
begin
if (DEBUG) begin
if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
read_data, address, expected);
end
else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1;
end
$display("");
@ -563,8 +558,10 @@ module tb_tk1();
write_word(ADDR_RAM_ADDR_RAND, 32'h13371337);
write_word(ADDR_RAM_DATA_RAND, 32'h47114711);
$display("--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x", dut.ram_addr_rand, dut.ram_data_rand);
$display(
"--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hf000000);
@ -573,8 +570,10 @@ module tb_tk1();
write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef);
write_word(ADDR_RAM_DATA_RAND, 32'hf00ff00f);
$display("--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x", dut.ram_addr_rand, dut.ram_data_rand);
$display(
"--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: completed.");
$display("");
@ -664,8 +663,8 @@ module tb_tk1();
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(2 * CLK_PERIOD);
$display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid);
$display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x", tb_cpu_addr,
tb_cpu_instr, tb_cpu_valid);
$display("--- test9: force_trap: 0x%1x", tb_force_trap);
$display("--- test9: completed.");
@ -719,8 +718,7 @@ module tb_tk1();
//----------------------------------------------------------------
// tk1_test
//----------------------------------------------------------------
initial
begin : tk1_test
initial begin : tk1_test
$display("");
$display(" -= Testbench for tk1 started =-");
$display(" ===========================");

126
hw/application_fpga/core/tk1/tb/tb_tk1_spi_master.v
View File

@ -11,10 +11,9 @@
//
//======================================================================
`default_nettype none
`timescale 1ns / 1ns
`default_nettype none `timescale 1ns / 1ns
module tb_tk1_spi_master();
module tb_tk1_spi_master ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -48,15 +47,15 @@ module tb_tk1_spi_master();
reg tb_spi_enable;
reg tb_spi_enable_vld;
reg tb_spi_start;
reg [7 : 0] tb_spi_tx_data;
reg [ 7 : 0] tb_spi_tx_data;
reg tb_spi_tx_data_vld;
wire [7 : 0] tb_spi_rx_data;
wire [ 7 : 0] tb_spi_rx_data;
wire tb_spi_ready;
wire mem_model_WPn;
wire mem_model_HOLDn;
reg [1 : 0] tb_miso_mux_ctrl;
reg [ 1 : 0] tb_miso_mux_ctrl;
reg my_tb_spi_ss;
@ -70,12 +69,12 @@ module tb_tk1_spi_master();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
tk1_spi_master dut(
tk1_spi_master dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
.spi_ss(tb_spi_ss),
.spi_sck(tb_spi_sck),
.spi_ss (tb_spi_ss),
.spi_sck (tb_spi_sck),
.spi_mosi(tb_spi_mosi),
.spi_miso(tb_spi_miso),
@ -92,7 +91,7 @@ module tb_tk1_spi_master();
//----------------------------------------------------------------
// spi_memory
//----------------------------------------------------------------
W25Q80DL spi_memory(
W25Q80DL spi_memory (
.CSn(tb_spi_ss),
.CLK(tb_spi_sck),
.DIO(tb_spi_mosi),
@ -107,8 +106,7 @@ module tb_tk1_spi_master();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -120,12 +118,10 @@ module tb_tk1_spi_master();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (monitor)
begin
if (monitor) begin
dump_dut_state();
end
end
@ -142,14 +138,12 @@ module tb_tk1_spi_master();
$display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------");
$display("Inputs and outputs:");
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x",
dut.spi_ss, dut.spi_sck, dut.spi_mosi, dut.spi_miso);
$display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x",
dut.spi_enable_vld, dut.spi_enable);
$display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x",
dut.spi_tx_data_vld, dut.spi_tx_data);
$display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x",
dut.spi_start, dut.spi_ready, dut.spi_rx_data);
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x", dut.spi_ss,
dut.spi_sck, dut.spi_mosi, dut.spi_miso);
$display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x", dut.spi_enable_vld, dut.spi_enable);
$display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x", dut.spi_tx_data_vld, dut.spi_tx_data);
$display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x", dut.spi_start,
dut.spi_ready, dut.spi_rx_data);
$display("");
@ -158,35 +152,35 @@ module tb_tk1_spi_master();
$display("spi_bit_ctr_rst: 0x%1x, spi_bit_ctr_inc: 0x%1x, spi_bit_ctr_reg: 0x%02x",
dut.spi_bit_ctr_rst, dut.spi_bit_ctr_inc, dut.spi_bit_ctr_reg);
$display("");
$display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x",
dut.spi_ctrl_reg, dut.spi_ctrl_new, dut.spi_ctrl_we);
$display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x", dut.spi_ctrl_reg,
dut.spi_ctrl_new, dut.spi_ctrl_we);
$display("");
$display("spi_tx_data_new: 0x%1x, spi_tx_data_nxt: 0x%1x, spi_tx_data_we: 0x%1x",
dut.spi_tx_data_new, dut.spi_tx_data_nxt, dut.spi_tx_data_we);
$display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x",
dut.spi_tx_data_reg, dut.spi_tx_data_new);
$display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x", dut.spi_tx_data_reg,
dut.spi_tx_data_new);
$display("");
$display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x",
dut.spi_rx_data_nxt, dut.spi_rx_data_we);
$display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x",
dut.spi_rx_data_reg, dut.spi_rx_data_new);
$display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x",
dut.spi_rx_data_reg[0], dut.spi_rx_data_new[0]);
$display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x",
dut.spi_rx_data_reg[1], dut.spi_rx_data_new[1]);
$display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x",
dut.spi_rx_data_reg[2], dut.spi_rx_data_new[2]);
$display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x",
dut.spi_rx_data_reg[3], dut.spi_rx_data_new[3]);
$display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x",
dut.spi_rx_data_reg[4], dut.spi_rx_data_new[4]);
$display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x",
dut.spi_rx_data_reg[5], dut.spi_rx_data_new[5]);
$display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x",
dut.spi_rx_data_reg[6], dut.spi_rx_data_new[6]);
$display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x",
dut.spi_rx_data_reg[7], dut.spi_rx_data_new[7]);
$display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x", dut.spi_rx_data_nxt,
dut.spi_rx_data_we);
$display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x", dut.spi_rx_data_reg,
dut.spi_rx_data_new);
$display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x", dut.spi_rx_data_reg[0],
dut.spi_rx_data_new[0]);
$display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x", dut.spi_rx_data_reg[1],
dut.spi_rx_data_new[1]);
$display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x", dut.spi_rx_data_reg[2],
dut.spi_rx_data_new[2]);
$display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x", dut.spi_rx_data_reg[3],
dut.spi_rx_data_new[3]);
$display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x", dut.spi_rx_data_reg[4],
dut.spi_rx_data_new[4]);
$display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x", dut.spi_rx_data_reg[5],
dut.spi_rx_data_new[5]);
$display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x", dut.spi_rx_data_reg[6],
dut.spi_rx_data_new[6]);
$display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x", dut.spi_rx_data_reg[7],
dut.spi_rx_data_new[7]);
$display("");
end
endtask // dump_dut_state
@ -214,12 +208,10 @@ module tb_tk1_spi_master();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
@ -306,7 +298,7 @@ module tb_tk1_spi_master();
// Wait until the SPI-master is ready, then send input byte
// and return the received byte.
//----------------------------------------------------------------
task xfer_byte (input [7 : 0] to_mem, output [7 : 0] from_mem);
task xfer_byte(input [7 : 0] to_mem, output [7 : 0] from_mem);
begin
if (verbose) begin
$display("xfer_byte: Trying to send 0x%02x to mem", to_mem);
@ -347,13 +339,14 @@ module tb_tk1_spi_master();
//
// Read out a specified memory range. Result is printed,
//----------------------------------------------------------------
task read_mem_range (input [23 : 0] address, input integer num_bytes);
task read_mem_range(input [23 : 0] address, input integer num_bytes);
begin : read_mem_range
reg [7 : 0] rx_byte;
integer i;
if (verbose) begin
$display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes, address);
$display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes,
address);
end
#(2 * CLK_PERIOD);
@ -369,7 +362,7 @@ module tb_tk1_spi_master();
xfer_byte(address[7 : 0], rx_byte);
// Read out num_bytes bytes.
for (i = 0 ; i < num_bytes ; i = i + 1) begin
for (i = 0; i < num_bytes; i = i + 1) begin
xfer_byte(8'h00, rx_byte);
$display("--- tc_read_mem_range: Byte 0x%06x: 0x%02x", address + i, rx_byte);
end
@ -387,9 +380,9 @@ module tb_tk1_spi_master();
//----------------------------------------------------------------
// read_status()
//----------------------------------------------------------------
task read_status ();
task read_status();
begin : read_status
reg [7 : 0] dummy;
reg [ 7 : 0] dummy;
reg [15 : 0] status;
enable_spi();
#(2 * CLK_PERIOD);
@ -531,7 +524,7 @@ module tb_tk1_spi_master();
// Send eight bytes and get unique device id back.
$display("--- tc_get_unique_device_id: reading out the unique device ID");
for (i = 0 ; i < 8 ; i = i + 1) begin
for (i = 0; i < 8; i = i + 1) begin
xfer_byte(8'h00, rx_byte);
$display("--- tc_get_unique_device_id: 0x%02x", rx_byte);
end
@ -624,7 +617,7 @@ module tb_tk1_spi_master();
// Read out 16 bytes.
$display("--- tc_read_mem: Reading out 16 bytes from the memory.");
for (i = 1 ; i < 17 ; i = i + 1) begin
for (i = 1; i < 17; i = i + 1) begin
xfer_byte(8'h00, rx_byte);
$display("--- tc_read_mem: Byte %d: 0x%02x", i, rx_byte);
end
@ -663,9 +656,9 @@ module tb_tk1_spi_master();
// Set write enable mode.
enable_spi();
// #(2 * CLK_PERIOD);
// #(2 * CLK_PERIOD);
xfer_byte(8'h06, rx_byte);
// #(2 * CLK_PERIOD);
// #(2 * CLK_PERIOD);
disable_spi();
#(2 * CLK_PERIOD);
$display("--- tc_rmr_mem: Status after write enable:");
@ -695,8 +688,7 @@ module tb_tk1_spi_master();
//----------------------------------------------------------------
// tk1_spi_master_test
//----------------------------------------------------------------
initial
begin : tk1_spi_master_test
initial begin : tk1_spi_master_test
$display("");
$display(" -= Testbench for tk1_spi_master started =-");
$display(" =======================================");
@ -708,12 +700,12 @@ module tb_tk1_spi_master();
verbose = 1;
// tc_get_device_id();
// tc_get_device_id();
tc_get_jedec_id();
// tc_get_manufacturer_id();
// tc_get_manufacturer_id();
tc_get_unique_device_id();
tc_read_mem();
// tc_rmr_mem();
// tc_rmr_mem();
display_test_result();
$display("");

7
hw/application_fpga/core/tk1/tb/udi_rom_sim.v
View File

@ -12,15 +12,14 @@
//======================================================================
module udi_rom (
input wire [0:0] addr,
input wire [ 0:0] addr,
output wire [31:0] data
);
);
reg [31 : 0] tmp_data;
assign data = tmp_data;
always @*
begin : addr_mux
always @* begin : addr_mux
if (addr) begin
tmp_data = 32'h04050607;
end

26
hw/application_fpga/core/touch_sense/rtl/touch_sense.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module touch_sense(
module touch_sense (
input wire clk,
input wire reset_n,
@ -22,10 +22,10 @@ module touch_sense(
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [ 7 : 0] address,
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -51,8 +51,8 @@ module touch_sense(
reg touch_event_rst;
reg touch_event_we;
reg [1 : 0] touch_sense_ctrl_reg;
reg [1 : 0] touch_sense_ctrl_new;
reg [ 1 : 0] touch_sense_ctrl_reg;
reg [ 1 : 0] touch_sense_ctrl_new;
reg touch_sense_ctrl_we;
@ -74,8 +74,7 @@ module touch_sense(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
touch_sense_ctrl_reg <= CTRL_IDLE;
touch_event_sample0_reg <= 1'h0;
@ -101,8 +100,7 @@ module touch_sense(
//----------------------------------------------------------------
// api
//----------------------------------------------------------------
always @*
begin : api
always @* begin : api
api_clear_event = 1'h0;
tmp_read_data = 32'h0;
tmp_ready = 1'h0;
@ -128,8 +126,7 @@ module touch_sense(
//----------------------------------------------------------------
// touch_event_reg_logic
//----------------------------------------------------------------
always @*
begin : touch_event_reg_logic
always @* begin : touch_event_reg_logic
touch_event_new = 1'h0;
touch_event_we = 1'h0;
@ -148,15 +145,14 @@ module touch_sense(
//----------------------------------------------------------------
// touch_sense_ctrl
//----------------------------------------------------------------
always @*
begin : touch_sense_ctrl
always @* begin : touch_sense_ctrl
touch_event_set = 1'h0;
touch_event_rst = 1'h0;
touch_sense_ctrl_new = CTRL_IDLE;
touch_sense_ctrl_we = 1'h0;
case (touch_sense_ctrl_reg)
CTRL_IDLE : begin
CTRL_IDLE: begin
if (touch_event_sample1_reg) begin
touch_event_set = 1'h1;
touch_sense_ctrl_new = CTRL_EVENT;
@ -179,7 +175,7 @@ module touch_sense(
end
end
default : begin
default: begin
end
endcase // case (touch_sense_ctrl_reg)
end

36
hw/application_fpga/core/touch_sense/tb/tb_touch_sense.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tb_touch_sense();
module tb_touch_sense ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -41,7 +41,7 @@ module tb_touch_sense();
reg tb_touch_event;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [ 7 : 0] tb_address;
wire [31 : 0] tb_read_data;
reg [31 : 0] read_data;
@ -50,7 +50,7 @@ module tb_touch_sense();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
touch_sense dut(
touch_sense dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
@ -68,8 +68,7 @@ module tb_touch_sense();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -81,12 +80,10 @@ module tb_touch_sense();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
if (tb_monitor) begin
dump_dut_state();
end
end
@ -129,12 +126,10 @@ module tb_touch_sense();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
@ -170,11 +165,9 @@ module tb_touch_sense();
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
task write_word(input [7 : 0] address, input [31 : 0] word);
begin
if (DEBUG) begin
$display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
@ -205,8 +198,7 @@ module tb_touch_sense();
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
if (DEBUG) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
@ -222,8 +214,7 @@ module tb_touch_sense();
task wait_ready;
begin : wready
read_word(ADDR_STATUS);
while (read_data == 0)
read_word(ADDR_STATUS);
while (read_data == 0) read_word(ADDR_STATUS);
end
endtask // wait_ready
@ -285,8 +276,7 @@ module tb_touch_sense();
//----------------------------------------------------------------
// touch_sense_test
//----------------------------------------------------------------
initial
begin : timer_test
initial begin : timer_test
$display("");
$display(" -= Testbench for touch_sense started =-");
$display(" ====================================");

65
hw/application_fpga/core/trng/rtl/rosc.v
View File

@ -16,19 +16,19 @@
`default_nettype none
module rosc(
module rosc (
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [ 7 : 0] address,
/* verilator lint_off UNUSED */
input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -51,41 +51,41 @@ module rosc(
//----------------------------------------------------------------
// Registers with associated wires.
//----------------------------------------------------------------
reg [15 : 0] cycle_ctr_reg;
reg [15 : 0] cycle_ctr_new;
reg [ 15 : 0] cycle_ctr_reg;
reg [ 15 : 0] cycle_ctr_new;
reg cycle_ctr_done;
reg cycle_ctr_rst;
reg [7 : 0] bit_ctr_reg;
reg [7 : 0] bit_ctr_new;
reg [ 7 : 0] bit_ctr_reg;
reg [ 7 : 0] bit_ctr_new;
reg bit_ctr_inc;
reg bit_ctr_rst;
reg bit_ctr_we;
reg [31 : 0] entropy_reg;
reg [31 : 0] entropy_new;
reg [ 31 : 0] entropy_reg;
reg [ 31 : 0] entropy_new;
reg entropy_we;
reg [1 : 0] sample1_reg;
reg [1 : 0] sample1_new;
reg [ 1 : 0] sample1_reg;
reg [ 1 : 0] sample1_new;
reg sample1_we;
reg [1 : 0] sample2_reg;
reg [1 : 0] sample2_new;
reg [ 1 : 0] sample2_reg;
reg [ 1 : 0] sample2_new;
reg sample2_we;
reg data_ready_reg;
reg data_ready_new;
reg data_ready_we;
reg [1 : 0] rosc_ctrl_reg;
reg [1 : 0] rosc_ctrl_new;
reg [ 1 : 0] rosc_ctrl_reg;
reg [ 1 : 0] rosc_ctrl_new;
reg rosc_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg [ 31 : 0] tmp_read_data;
reg tmp_ready;
/* verilator lint_off UNOPTFLAT */
@ -111,13 +111,23 @@ module rosc(
//----------------------------------------------------------------
genvar i;
generate
for(i = 0 ; i < NUM_ROSC ; i = i + 1)
begin: oscillators
for (i = 0; i < NUM_ROSC; i = i + 1) begin : oscillators
/* verilator lint_off PINMISSING */
/* verilator lint_off UNOPTFLAT */
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_f (.I0(f[i]), .O(f[i]));
(* keep *)
SB_LUT4 #(
.LUT_INIT(16'h1)
) osc_inv_f (
.I0(f[i]),
.O (f[i])
);
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_g (.I0(g[i]), .O(g[i]));
(* keep *) SB_LUT4 #(
.LUT_INIT(16'h1)
) osc_inv_g (
.I0(g[i]),
.O (g[i])
);
/* verilator lint_on UNOPTFLAT */
/* verilator lint_on PINMISSING */
end
@ -127,8 +137,7 @@ module rosc(
//---------------------------------------------------------------
// reg_update
//---------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
cycle_ctr_reg <= 16'h0;
bit_ctr_reg <= 8'h0;
@ -174,8 +183,7 @@ module rosc(
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
always @* begin : api
bit_ctr_rst = 1'h0;
tmp_read_data = 32'h0;
tmp_ready = 1'h0;
@ -200,8 +208,7 @@ module rosc(
//----------------------------------------------------------------
// bit_ctr_logic
//----------------------------------------------------------------
always @*
begin : bit_ctr_logic
always @* begin : bit_ctr_logic
bit_ctr_new = 8'h0;
bit_ctr_we = 1'h0;
data_ready_new = 1'h0;
@ -228,8 +235,7 @@ module rosc(
//----------------------------------------------------------------
// cycle_ctr_logic
//----------------------------------------------------------------
always @*
begin : cycle_ctr_logic
always @* begin : cycle_ctr_logic
cycle_ctr_new = cycle_ctr_reg + 1'h1;
cycle_ctr_done = 1'h0;
@ -246,8 +252,7 @@ module rosc(
//----------------------------------------------------------------
// rosc_ctrl_logic
//----------------------------------------------------------------
always @*
begin : rosc_ctrl_logic
always @* begin : rosc_ctrl_logic
reg xor_f;
reg xor_g;
reg xor_sample1;

2
hw/application_fpga/core/trng/tb/SB_LUT4.v
View File

@ -16,7 +16,7 @@
module SB_LUT4 (
input wire I0,
output wire O
);
);
parameter LUT_INIT = 16'h0;

34
hw/application_fpga/core/trng/tb/tb_trng.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tb_trng();
module tb_trng ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -41,7 +41,7 @@ module tb_trng();
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_ready;
@ -50,7 +50,7 @@ module tb_trng();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
rosc dut(
rosc dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
@ -68,8 +68,7 @@ module tb_trng();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -81,12 +80,10 @@ module tb_trng();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
if (tb_monitor) begin
dump_dut_state();
end
end
@ -139,12 +136,10 @@ module tb_trng();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
@ -195,13 +190,13 @@ module tb_trng();
#(CLK_HALF_PERIOD);
tb_cs = 1'h0;
if (DEBUG)
begin
if (DEBUG) begin
if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
read_data, address, expected);
end
else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1;
end
$display("");
@ -230,8 +225,7 @@ module tb_trng();
//----------------------------------------------------------------
// trng_test
//----------------------------------------------------------------
initial
begin : trng_test
initial begin : trng_test
$display("");
$display(" -= Testbench for trng started =-");
$display(" ============================");

46
hw/application_fpga/core/uart/rtl/uart.v
View File

@ -48,7 +48,7 @@
//
//======================================================================
module uart(
module uart (
input wire clk,
input wire reset_n,
@ -57,13 +57,13 @@ module uart(
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [ 7 : 0] address,
/* verilator lint_off UNUSED */
input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -97,10 +97,10 @@ module uart(
reg [15 : 0] bit_rate_reg;
reg bit_rate_we;
reg [3 : 0] data_bits_reg;
reg [ 3 : 0] data_bits_reg;
reg data_bits_we;
reg [1 : 0] stop_bits_reg;
reg [ 1 : 0] stop_bits_reg;
reg stop_bits_we;
@ -108,17 +108,17 @@ module uart(
// Wires.
//----------------------------------------------------------------
wire core_rxd_syn;
wire [7 : 0] core_rxd_data;
wire [ 7 : 0] core_rxd_data;
wire core_rxd_ack;
reg core_txd_syn;
reg [7 : 0] core_txd_data;
reg [ 7 : 0] core_txd_data;
wire core_txd_ready;
wire fifo_out_syn;
wire [7 : 0] fifo_out_data;
wire [ 7 : 0] fifo_out_data;
reg fifo_out_ack;
wire [8 : 0] fifo_bytes;
wire [ 8 : 0] fifo_bytes;
reg [31 : 0] tmp_read_data;
reg tmp_ready;
@ -134,12 +134,12 @@ module uart(
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
uart_core core(
uart_core core (
.clk(clk),
.reset_n(reset_n),
// Configuration parameters
.bit_rate(bit_rate_reg),
.bit_rate (bit_rate_reg),
.data_bits(data_bits_reg),
.stop_bits(stop_bits_reg),
@ -148,30 +148,30 @@ module uart(
.txd(txd),
// Internal receive interface.
.rxd_syn(core_rxd_syn),
.rxd_syn (core_rxd_syn),
.rxd_data(core_rxd_data),
.rxd_ack(core_rxd_ack),
.rxd_ack (core_rxd_ack),
// Internal transmit interface.
.txd_syn(core_txd_syn),
.txd_data(core_txd_data),
.txd_syn (core_txd_syn),
.txd_data (core_txd_data),
.txd_ready(core_txd_ready)
);
uart_fifo fifo(
uart_fifo fifo (
.clk(clk),
.reset_n(reset_n),
.in_syn(core_rxd_syn),
.in_syn (core_rxd_syn),
.in_data(core_rxd_data),
.in_ack(core_rxd_ack),
.in_ack (core_rxd_ack),
.fifo_bytes(fifo_bytes),
.out_syn(fifo_out_syn),
.out_syn (fifo_out_syn),
.out_data(fifo_out_data),
.out_ack(fifo_out_ack)
.out_ack (fifo_out_ack)
);
@ -182,8 +182,7 @@ module uart(
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin: reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
bit_rate_reg <= DEFAULT_BIT_RATE;
data_bits_reg <= DEFAULT_DATA_BITS;
@ -211,8 +210,7 @@ module uart(
// The core API that allows an internal host to control the
// core functionality.
//----------------------------------------------------------------
always @*
begin: api
always @* begin : api
// Default assignments.
bit_rate_we = 1'h0;
data_bits_we = 1'h0;

51
hw/application_fpga/core/uart/rtl/uart_core.v
View File

@ -46,14 +46,14 @@
//
//======================================================================
module uart_core(
module uart_core (
input wire clk,
input wire reset_n,
// Configuration parameters
input wire [15 : 0] bit_rate,
input wire [3 : 0] data_bits,
input wire [1 : 0] stop_bits,
input wire [ 3 : 0] data_bits,
input wire [ 1 : 0] stop_bits,
// External data interface
input wire rxd,
@ -68,7 +68,7 @@ module uart_core(
input wire txd_syn,
input wire [7 : 0] txd_data,
output wire txd_ready
);
);
//----------------------------------------------------------------
@ -93,11 +93,11 @@ module uart_core(
reg rxd0_reg;
reg rxd_reg;
reg [7 : 0] rxd_byte_reg;
reg [ 7 : 0] rxd_byte_reg;
reg rxd_byte_we;
reg [3 : 0] rxd_bit_ctr_reg;
reg [3 : 0] rxd_bit_ctr_new;
reg [ 3 : 0] rxd_bit_ctr_reg;
reg [ 3 : 0] rxd_bit_ctr_new;
reg rxd_bit_ctr_we;
reg rxd_bit_ctr_rst;
reg rxd_bit_ctr_inc;
@ -112,20 +112,20 @@ module uart_core(
reg rxd_syn_new;
reg rxd_syn_we;
reg [2 : 0] erx_ctrl_reg;
reg [2 : 0] erx_ctrl_new;
reg [ 2 : 0] erx_ctrl_reg;
reg [ 2 : 0] erx_ctrl_new;
reg erx_ctrl_we;
reg txd_reg;
reg txd_new;
reg txd_we;
reg [7 : 0] txd_byte_reg;
reg [7 : 0] txd_byte_new;
reg [ 7 : 0] txd_byte_reg;
reg [ 7 : 0] txd_byte_new;
reg txd_byte_we;
reg [3 : 0] txd_bit_ctr_reg;
reg [3 : 0] txd_bit_ctr_new;
reg [ 3 : 0] txd_bit_ctr_reg;
reg [ 3 : 0] txd_bit_ctr_new;
reg txd_bit_ctr_we;
reg txd_bit_ctr_rst;
reg txd_bit_ctr_inc;
@ -140,8 +140,8 @@ module uart_core(
reg txd_ready_new;
reg txd_ready_we;
reg [2 : 0] etx_ctrl_reg;
reg [2 : 0] etx_ctrl_new;
reg [ 2 : 0] etx_ctrl_reg;
reg [ 2 : 0] etx_ctrl_new;
reg etx_ctrl_we;
@ -169,8 +169,7 @@ module uart_core(
// All registers are positive edge triggered with
// synchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin: reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
rxd0_reg <= 1'b0;
rxd_reg <= 1'b0;
@ -245,8 +244,7 @@ module uart_core(
// Bit counter for receiving data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: rxd_bit_ctr
always @* begin : rxd_bit_ctr
rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b0;
@ -268,8 +266,7 @@ module uart_core(
// Bitrate counter for receiving data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: rxd_bitrate_ctr
always @* begin : rxd_bitrate_ctr
rxd_bitrate_ctr_new = 16'h0;
rxd_bitrate_ctr_we = 1'h0;
@ -292,8 +289,7 @@ module uart_core(
// Bit counter for transmitting data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: txd_bit_ctr
always @* begin : txd_bit_ctr
txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h0;
@ -315,8 +311,7 @@ module uart_core(
// Bitrate counter for transmitting data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: txd_bitrate_ctr
always @* begin : txd_bitrate_ctr
txd_bitrate_ctr_new = 16'h0;
txd_bitrate_ctr_we = 0;
@ -340,8 +335,7 @@ module uart_core(
// if required checks parity and store correct data into
// the rx buffer.
//----------------------------------------------------------------
always @*
begin: external_rx_engine
always @* begin : external_rx_engine
rxd_bit_ctr_rst = 0;
rxd_bit_ctr_inc = 0;
rxd_bitrate_ctr_rst = 0;
@ -432,8 +426,7 @@ module uart_core(
// Logic that implements the transmit engine towards
// the external interface.
//----------------------------------------------------------------
always @*
begin: external_tx_engine
always @* begin : external_tx_engine
txd_new = 0;
txd_we = 0;
txd_byte_new = 0;

28
hw/application_fpga/core/uart/rtl/uart_fifo.v
View File

@ -36,7 +36,7 @@
//
//======================================================================
module uart_fifo(
module uart_fifo (
input wire clk,
input wire reset_n,
@ -49,7 +49,7 @@ module uart_fifo(
output wire out_syn,
output wire [7 : 0] out_data,
input wire out_ack
);
);
//----------------------------------------------------------------
@ -58,16 +58,16 @@ module uart_fifo(
reg [7 : 0] fifo_mem [0 : 511];
reg fifo_mem_we;
reg [8: 0] in_ptr_reg;
reg [8: 0] in_ptr_new;
reg [ 8:0] in_ptr_reg;
reg [ 8:0] in_ptr_new;
reg in_ptr_we;
reg [8: 0] out_ptr_reg;
reg [8: 0] out_ptr_new;
reg [ 8:0] out_ptr_reg;
reg [ 8:0] out_ptr_new;
reg out_ptr_we;
reg [8: 0] byte_ctr_reg;
reg [8: 0] byte_ctr_new;
reg [ 8:0] byte_ctr_reg;
reg [ 8:0] byte_ctr_new;
reg byte_ctr_inc;
reg byte_ctr_dec;
reg byte_ctr_we;
@ -95,8 +95,7 @@ module uart_fifo(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin: reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
in_ptr_reg <= 9'h0;
out_ptr_reg <= 9'h0;
@ -128,8 +127,7 @@ module uart_fifo(
//----------------------------------------------------------------
// byte_ctr
//----------------------------------------------------------------
always @*
begin : byte_ctr
always @* begin : byte_ctr
fifo_empty = 1'h0;
fifo_full = 1'h0;
byte_ctr_new = 9'h0;
@ -158,8 +156,7 @@ module uart_fifo(
//----------------------------------------------------------------
// in_logic
//----------------------------------------------------------------
always @*
begin : in_logic
always @* begin : in_logic
fifo_mem_we = 1'h0;
in_ack_new = 1'h0;
byte_ctr_inc = 1'h0;
@ -179,8 +176,7 @@ module uart_fifo(
//----------------------------------------------------------------
// out_logic
//----------------------------------------------------------------
always @*
begin : out_logic
always @* begin : out_logic
byte_ctr_dec = 1'h0;
out_ptr_we = 1'h0;

64
hw/application_fpga/core/uart/tb/tb_uart.v
View File

@ -36,7 +36,7 @@
//
//======================================================================
module tb_uart();
module tb_uart ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -61,7 +61,7 @@ module tb_uart();
wire tb_txd;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_ready;
@ -72,7 +72,7 @@ module tb_uart();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
uart dut(
uart dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
@ -99,8 +99,7 @@ module tb_uart();
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
@ -108,17 +107,14 @@ module tb_uart();
//----------------------------------------------------------------
// sys_monitor
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
#(CLK_PERIOD);
if (DEBUG)
begin
if (DEBUG) begin
dump_rx_state();
dump_tx_state();
$display("");
end
if (VERBOSE)
begin
if (VERBOSE) begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
@ -130,16 +126,13 @@ module tb_uart();
//
// Observes what happens on the dut tx port and reports it.
//----------------------------------------------------------------
always @*
begin : tx_monitor
if ((!tb_txd) && txd_state)
begin
always @* begin : tx_monitor
if ((!tb_txd) && txd_state) begin
$display("txd going low.");
txd_state = 0;
end
if (tb_txd && (!txd_state))
begin
if (tb_txd && (!txd_state)) begin
$display("txd going high");
txd_state = 1;
end
@ -156,24 +149,21 @@ module tb_uart();
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("rxd = 0x%01x, txd = 0x%01x,",
dut.core.rxd, dut.core.txd);
$display("rxd = 0x%01x, txd = 0x%01x,", dut.core.rxd, dut.core.txd);
$display("");
$display("Sample and data registers:");
$display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x",
dut.core.rxd_reg, dut.core.rxd_byte_reg);
$display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x", dut.core.rxd_reg, dut.core.rxd_byte_reg);
$display("");
$display("Counters:");
$display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x",
dut.core.rxd_bit_ctr_reg, dut.core.rxd_bitrate_ctr_reg);
$display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x", dut.core.rxd_bit_ctr_reg,
dut.core.rxd_bitrate_ctr_reg);
$display("");
$display("Control signals and FSM state:");
$display("erx_ctrl_reg = 0x%02x",
dut.core.erx_ctrl_reg);
$display("erx_ctrl_reg = 0x%02x", dut.core.erx_ctrl_reg);
$display("");
end
endtask // dump_dut_state
@ -187,7 +177,8 @@ module tb_uart();
//----------------------------------------------------------------
task dump_rx_state;
begin
$display("rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x",
$display(
"rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x",
dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg,
dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg);
end
@ -262,8 +253,7 @@ module tb_uart();
#(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
// Send the bits LSB first.
for (i = 0 ; i < 8 ; i = i + 1)
begin
for (i = 0; i < 8; i = i + 1) begin
$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
tb_rxd = data[i];
#(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
@ -290,13 +280,10 @@ module tb_uart();
transmit_byte(data);
if (dut.core.rxd_byte_reg == data)
begin
$display("*** Correct data: 0x%01x captured by the dut.",
dut.core.rxd_byte_reg);
if (dut.core.rxd_byte_reg == data) begin
$display("*** Correct data: 0x%01x captured by the dut.", dut.core.rxd_byte_reg);
end
else
begin
else begin
$display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
dut.core.rxd_byte_reg, data);
error_ctr = error_ctr + 1;
@ -327,12 +314,10 @@ module tb_uart();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
@ -343,8 +328,7 @@ module tb_uart();
// uart_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : uart_test
initial begin : uart_test
$display(" -- Testbench for uart core started --");
init_sim();

20
hw/application_fpga/core/uds/rtl/uds.v
View File

@ -13,17 +13,17 @@
`default_nettype none
module uds(
module uds (
input wire clk,
input wire reset_n,
input wire fw_app_mode,
input wire cs,
input wire [2 : 0] address,
input wire [ 2 : 0] address,
output wire [31 : 0] read_data,
output wire ready
);
);
//----------------------------------------------------------------
@ -50,9 +50,9 @@ module uds(
//----------------------------------------------------------------
// uds rom instance.
//----------------------------------------------------------------
uds_rom rom_i(
uds_rom rom_i (
.addr(address),
.re(uds_rd_we),
.re (uds_rd_we),
.data(tmp_read_data)
);
@ -61,13 +61,12 @@ module uds(
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
integer i;
if (!reset_n) begin
for (i = 0 ; i < 8 ; i = i + 1) begin
uds_rd_reg[i] <= 1'h0;;
for (i = 0; i < 8; i = i + 1) begin
uds_rd_reg[i] <= 1'h0;
end
end
else begin
@ -83,8 +82,7 @@ module uds(
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
always @* begin : api
uds_rd_we = 1'h0;
tmp_ready = 1'h0;

16
hw/application_fpga/core/uds/rtl/uds_rom.v
View File

@ -14,21 +14,23 @@
`default_nettype none
module uds_rom(
module uds_rom (
input wire [2:0] addr,
input wire re,
output wire [31:0] data
);
);
generate
genvar ii;
for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts
(* uds_rom_idx=ii, keep *) SB_LUT4
#(
for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts
(* uds_rom_idx=ii, keep *) SB_LUT4 #(
.LUT_INIT({8'ha6 ^ ii[7:0], 8'h00})
) lut_i (
.I0(addr[0]), .I1(addr[1]), .I2(addr[2]), .I3(re),
.O(data[ii])
.I0(addr[0]),
.I1(addr[1]),
.I2(addr[2]),
.I3(re),
.O (data[ii])
);
end
endgenerate

39
hw/application_fpga/core/uds/tb/tb_uds.v
View File

@ -13,7 +13,7 @@
`default_nettype none
module tb_uds();
module tb_uds ();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@ -39,14 +39,14 @@ module tb_uds();
reg tb_reset_n;
reg tb_fw_app_mode;
reg tb_cs;
reg [7 : 0] tb_address;
reg [ 7 : 0] tb_address;
wire [31 : 0] tb_read_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
uds dut(
uds dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
@ -63,8 +63,7 @@ module tb_uds();
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
always begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
@ -76,12 +75,10 @@ module tb_uds();
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
always begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
if (tb_monitor) begin
dump_dut_state();
end
end
@ -104,8 +101,9 @@ module tb_uds();
$display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
for (i = 0 ; i < 8 ; i = i + 1) begin
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
for (i = 0; i < 8; i = i + 1) begin
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i,
dut.uds_rd_reg[i]);
end
$display("");
@ -136,12 +134,10 @@ module tb_uds();
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
else begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
@ -191,13 +187,13 @@ module tb_uds();
#(CLK_HALF_PERIOD);
tb_cs = 1'h0;
if (DEBUG)
begin
if (DEBUG) begin
if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
read_data, address, expected);
end
else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1;
end
$display("");
@ -306,8 +302,7 @@ module tb_uds();
//----------------------------------------------------------------
// uds_test
//----------------------------------------------------------------
initial
begin : uds_test
initial begin : uds_test
$display("");
$display(" -= Testbench for uds started =-");
$display(" ===========================");

71
hw/application_fpga/rtl/application_fpga.v
View File

@ -16,7 +16,7 @@
`default_nettype none
module application_fpga(
module application_fpga (
output wire interface_rx,
input wire interface_tx,
@ -35,7 +35,7 @@ module application_fpga(
output wire led_r,
output wire led_g,
output wire led_b
);
);
//----------------------------------------------------------------
@ -91,7 +91,7 @@ module application_fpga(
wire rom_ready;
reg ram_cs;
reg [3 : 0] ram_we;
reg [ 3 : 0] ram_we;
reg [15 : 0] ram_address;
reg [31 : 0] ram_write_data;
wire [31 : 0] ram_read_data;
@ -99,46 +99,46 @@ module application_fpga(
reg trng_cs;
reg trng_we;
reg [7 : 0] trng_address;
reg [ 7 : 0] trng_address;
reg [31 : 0] trng_write_data;
wire [31 : 0] trng_read_data;
wire trng_ready;
reg timer_cs;
reg timer_we;
reg [7 : 0] timer_address;
reg [ 7 : 0] timer_address;
reg [31 : 0] timer_write_data;
wire [31 : 0] timer_read_data;
wire timer_ready;
reg uds_cs;
reg [2 : 0] uds_address;
reg [ 2 : 0] uds_address;
wire [31 : 0] uds_read_data;
wire uds_ready;
reg uart_cs;
reg uart_we;
reg [7 : 0] uart_address;
reg [ 7 : 0] uart_address;
reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data;
wire uart_ready;
reg fw_ram_cs;
reg [3 : 0] fw_ram_we;
reg [8 : 0] fw_ram_address;
reg [ 3 : 0] fw_ram_we;
reg [ 8 : 0] fw_ram_address;
reg [31 : 0] fw_ram_write_data;
wire [31 : 0] fw_ram_read_data;
wire fw_ram_ready;
reg touch_sense_cs;
reg touch_sense_we;
reg [7 : 0] touch_sense_address;
reg [ 7 : 0] touch_sense_address;
wire [31 : 0] touch_sense_read_data;
wire touch_sense_ready;
reg tk1_cs;
reg tk1_we;
reg [7 : 0] tk1_address;
reg [ 7 : 0] tk1_address;
reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data;
wire tk1_ready;
@ -153,8 +153,9 @@ module application_fpga(
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
clk_reset_gen #(.RESET_CYCLES(200))
reset_gen_inst(
clk_reset_gen #(
.RESET_CYCLES(200)
) reset_gen_inst (
.sys_reset(tk1_system_reset),
.clk(clk),
.rst_n(reset_n)
@ -164,11 +165,11 @@ module application_fpga(
picorv32 #(
.ENABLE_COUNTERS(0),
.TWO_STAGE_SHIFT(0),
.CATCH_MISALIGN(0),
.COMPRESSED_ISA(1),
.CATCH_MISALIGN (0),
.COMPRESSED_ISA (1),
.ENABLE_FAST_MUL(1),
.BARREL_SHIFTER(1)
) cpu(
.BARREL_SHIFTER (1)
) cpu (
.clk(clk),
.resetn(reset_n),
.trap(cpu_trap),
@ -205,7 +206,7 @@ module application_fpga(
);
rom rom_inst(
rom rom_inst (
.clk(clk),
.reset_n(reset_n),
@ -216,7 +217,7 @@ module application_fpga(
);
ram ram_inst(
ram ram_inst (
.clk(clk),
.reset_n(reset_n),
@ -232,7 +233,7 @@ module application_fpga(
);
fw_ram fw_ram_inst(
fw_ram fw_ram_inst (
.clk(clk),
.reset_n(reset_n),
@ -247,7 +248,7 @@ module application_fpga(
);
rosc trng_inst(
rosc trng_inst (
.clk(clk),
.reset_n(reset_n),
.cs(trng_cs),
@ -259,7 +260,7 @@ module application_fpga(
);
timer timer_inst(
timer timer_inst (
.clk(clk),
.reset_n(reset_n),
@ -272,7 +273,7 @@ module application_fpga(
);
uds uds_inst(
uds uds_inst (
.clk(clk),
.reset_n(reset_n),
@ -285,7 +286,7 @@ module application_fpga(
);
uart uart_inst(
uart uart_inst (
.clk(clk),
.reset_n(reset_n),
@ -301,7 +302,7 @@ module application_fpga(
);
touch_sense touch_sense_inst(
touch_sense touch_sense_inst (
.clk(clk),
.reset_n(reset_n),
@ -315,16 +316,16 @@ module application_fpga(
);
tk1 tk1_inst(
tk1 tk1_inst (
.clk(clk),
.reset_n(reset_n),
.fw_app_mode(fw_app_mode),
.cpu_addr(cpu_addr),
.cpu_instr(cpu_instr),
.cpu_valid(cpu_valid),
.cpu_trap(cpu_trap),
.cpu_addr (cpu_addr),
.cpu_instr (cpu_instr),
.cpu_valid (cpu_valid),
.cpu_trap (cpu_trap),
.force_trap(force_trap),
.system_reset(tk1_system_reset),
@ -332,8 +333,8 @@ module application_fpga(
.ram_addr_rand(ram_addr_rand),
.ram_data_rand(ram_data_rand),
.spi_ss(spi_ss),
.spi_sck(spi_sck),
.spi_ss (spi_ss),
.spi_sck (spi_sck),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
@ -359,8 +360,7 @@ module application_fpga(
// Reg_update.
// Posedge triggered with synchronous, active low reset.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
muxed_rdata_reg <= 32'h0;
muxed_ready_reg <= 1'h0;
@ -377,8 +377,7 @@ module application_fpga(
// cpu_mem_ctrl
// CPU memory decode and control logic.
//----------------------------------------------------------------
always @*
begin : cpu_mem_ctrl
always @* begin : cpu_mem_ctrl
reg [1 : 0] area_prefix;
reg [5 : 0] core_prefix;

52
hw/application_fpga/tb/application_fpga_vsim.v
View File

@ -18,13 +18,13 @@
//`define VERBOSE
`ifdef VERBOSE
`define verbose(debug_command) debug_command
`define verbose(debug_command) debug_command
`else
`define verbose(debug_command)
`define verbose(debug_command)
`endif
module application_fpga(
module application_fpga (
input wire clk,
output wire valid,
@ -47,7 +47,7 @@ module application_fpga(
output wire led_r,
output wire led_g,
output wire led_b
);
);
//----------------------------------------------------------------
@ -96,7 +96,7 @@ module application_fpga(
wire rom_ready;
reg ram_cs;
reg [3 : 0] ram_we;
reg [ 3 : 0] ram_we;
reg [14 : 0] ram_address;
reg [31 : 0] ram_write_data;
wire [31 : 0] ram_read_data;
@ -106,7 +106,7 @@ module application_fpga(
reg trng_cs;
/* verilator lint_on UNOPTFLAT */
reg trng_we;
reg [7 : 0] trng_address;
reg [ 7 : 0] trng_address;
reg [31 : 0] trng_write_data;
wire [31 : 0] trng_read_data;
wire trng_ready;
@ -115,7 +115,7 @@ module application_fpga(
reg timer_cs;
/* verilator lint_on UNOPTFLAT */
reg timer_we;
reg [7 : 0] timer_address;
reg [ 7 : 0] timer_address;
reg [31 : 0] timer_write_data;
wire [31 : 0] timer_read_data;
wire timer_ready;
@ -123,7 +123,7 @@ module application_fpga(
/* verilator lint_off UNOPTFLAT */
reg uds_cs;
/* verilator lint_on UNOPTFLAT */
reg [7 : 0] uds_address;
reg [ 7 : 0] uds_address;
wire [31 : 0] uds_read_data;
wire uds_ready;
@ -131,7 +131,7 @@ module application_fpga(
reg uart_cs;
/* verilator lint_on UNOPTFLAT */
reg uart_we;
reg [7 : 0] uart_address;
reg [ 7 : 0] uart_address;
reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data;
wire uart_ready;
@ -140,7 +140,7 @@ module application_fpga(
reg touch_sense_cs;
/* verilator lint_on UNOPTFLAT */
reg touch_sense_we;
reg [7 : 0] touch_sense_address;
reg [ 7 : 0] touch_sense_address;
wire [31 : 0] touch_sense_read_data;
wire touch_sense_ready;
@ -148,7 +148,7 @@ module application_fpga(
reg tk1_cs;
/* verilator lint_on UNOPTFLAT */
reg tk1_we;
reg [7 : 0] tk1_address;
reg [ 7 : 0] tk1_address;
reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data;
wire tk1_ready;
@ -169,8 +169,12 @@ module application_fpga(
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
reset_gen #(.RESET_CYCLES(200))
reset_gen_inst(.clk(clk), .rst_n(reset_n));
reset_gen #(
.RESET_CYCLES(200)
) reset_gen_inst (
.clk (clk),
.rst_n(reset_n)
);
picorv32 #(
@ -184,7 +188,7 @@ module application_fpga(
.ENABLE_MUL(1),
.ENABLE_DIV(0),
.BARREL_SHIFTER(0)
) cpu(
) cpu (
.clk(clk),
.resetn(reset_n),
@ -221,7 +225,7 @@ module application_fpga(
);
rom rom_inst(
rom rom_inst (
.cs(rom_cs),
.address(rom_address),
.read_data(rom_read_data),
@ -229,7 +233,7 @@ module application_fpga(
);
ram ram_inst(
ram ram_inst (
.clk(clk),
.reset_n(reset_n),
@ -242,7 +246,7 @@ module application_fpga(
);
timer timer_inst(
timer timer_inst (
.clk(clk),
.reset_n(reset_n),
@ -255,7 +259,7 @@ module application_fpga(
);
uds uds_inst(
uds uds_inst (
.clk(clk),
.reset_n(reset_n),
@ -266,7 +270,7 @@ module application_fpga(
);
uart uart_inst(
uart uart_inst (
.clk(clk),
.reset_n(reset_n),
@ -282,7 +286,7 @@ module application_fpga(
);
touch_sense touch_sense_inst(
touch_sense touch_sense_inst (
.clk(clk),
.reset_n(reset_n),
@ -296,7 +300,7 @@ module application_fpga(
);
tk1 tk1_inst(
tk1 tk1_inst (
.clk(clk),
.reset_n(reset_n),
@ -324,8 +328,7 @@ module application_fpga(
// Reg_update.
// Posedge triggered with synchronous, active low reset.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
if (!reset_n) begin
muxed_ready_reg <= 1'h0;
muxed_rdata_reg <= 32'h0;
@ -342,8 +345,7 @@ module application_fpga(
// cpu_mem_ctrl
// CPU memory decode and control logic.
//----------------------------------------------------------------
always @*
begin : cpu_mem_ctrl
always @* begin : cpu_mem_ctrl
reg [1 : 0] area_prefix;
reg [5 : 0] core_prefix;

16
hw/application_fpga/tb/reset_gen_vsim.v
View File

@ -13,11 +13,12 @@
`default_nettype none
module reset_gen #(parameter RESET_CYCLES = 200)
(
module reset_gen #(
parameter RESET_CYCLES = 200
) (
input wire clk,
output wire rst_n
);
);
//----------------------------------------------------------------
@ -40,20 +41,17 @@ module reset_gen #(parameter RESET_CYCLES = 200)
//----------------------------------------------------------------
// reg_update.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
always @(posedge clk) begin : reg_update
rst_n_reg <= rst_n_new;
if (rst_ctr_we)
rst_ctr_reg <= rst_ctr_new;
if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
end
//----------------------------------------------------------------
// rst_logic.
//----------------------------------------------------------------
always @*
begin : rst_logic
always @* begin : rst_logic
rst_n_new = 1'h1;
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;