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FPGA: Format verilog code

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This commit is contained in:
Jonas Thörnblad 2024-10-22 11:54:56 +02:00 committed by Daniel Jobson
parent e04aacda48
commit 3514d7ef3c
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GPG Key ID: 3707A9DBF4BB8F1A
30 changed files with 3477 additions and 3579 deletions
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109
hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
View File

@ -16,33 +16,34 @@
`default_nettype none `default_nettype none
module clk_reset_gen #(parameter RESET_CYCLES = 200) module clk_reset_gen #(
( parameter RESET_CYCLES = 200
input wire sys_reset, ) (
input wire sys_reset,
output wire clk, output wire clk,
output wire rst_n output wire rst_n
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers with associated wires. // Registers with associated wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [7 : 0] rst_ctr_reg = 8'h0; reg [7 : 0] rst_ctr_reg = 8'h0;
reg [7 : 0] rst_ctr_new; reg [7 : 0] rst_ctr_new;
reg rst_ctr_we; reg rst_ctr_we;
reg rst_n_reg = 1'h0; reg rst_n_reg = 1'h0;
reg rst_n_new; reg rst_n_new;
reg sys_reset_reg; reg sys_reset_reg;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
wire hfosc_clk; wire hfosc_clk;
wire pll_clk; wire pll_clk;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -58,8 +59,13 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
// Use the FPGA internal High Frequency OSCillator as clock source. // Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
SB_HFOSC #(.CLKHF_DIV("0b10") SB_HFOSC #(
) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk)); .CLKHF_DIV("0b10")
) hfosc_inst (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (hfosc_clk)
);
// Use a PLL to generate a new clock frequency based on the HFOSC clock. // Use a PLL to generate a new clock frequency based on the HFOSC clock.
@ -74,24 +80,24 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
// //
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000 // (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #( SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"), .FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0 .DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55 .DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5 .DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst ( ) pll_inst (
.RESETB(1'b1), .RESETB(1'b1),
.BYPASS(1'b0), .BYPASS(1'b0),
.REFERENCECLK(hfosc_clk), .REFERENCECLK(hfosc_clk),
.PLLOUTCORE(pll_clk) .PLLOUTCORE(pll_clk)
); );
// Use a Global Buffer to distribute the clock. // Use a Global Buffer to distribute the clock.
SB_GB gb_inst ( SB_GB gb_inst (
.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk), .USER_SIGNAL_TO_GLOBAL_BUFFER(pll_clk),
.GLOBAL_BUFFER_OUTPUT (clk) .GLOBAL_BUFFER_OUTPUT(clk)
); );
/* verilator lint_on PINMISSING */ /* verilator lint_on PINMISSING */
@ -99,38 +105,35 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update. // reg_update.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update rst_n_reg <= rst_n_new;
rst_n_reg <= rst_n_new; sys_reset_reg <= sys_reset;
sys_reset_reg <= sys_reset;
if (rst_ctr_we) if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
rst_ctr_reg <= rst_ctr_new; end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// rst_logic. // rst_logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rst_logic
begin : rst_logic rst_n_new = 1'h1;
rst_n_new = 1'h1; rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;
if (sys_reset_reg) begin
rst_ctr_new = 8'h0; rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0; rst_ctr_we = 1'h1;
if (sys_reset_reg) begin
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h1;
end
else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
end end
endmodule // reset_gen else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
end
endmodule // reset_gen
//====================================================================== //======================================================================
// EOF reset_gen.v // EOF reset_gen.v

184
hw/application_fpga/core/fw_ram/rtl/fw_ram.v
View File

@ -13,31 +13,31 @@
`default_nettype none `default_nettype none
module fw_ram( module fw_ram (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire fw_app_mode, input wire fw_app_mode,
input wire cs, input wire cs,
input wire [3 : 0] we, input wire [ 3 : 0] we,
input wire [8 : 0] address, input wire [ 8 : 0] address,
input wire [31 : 0] write_data, input wire [31 : 0] write_data,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers and wires. // Registers and wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] tmp_read_data; reg [31 : 0] tmp_read_data;
reg [31 : 0] mem_read_data0; reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1; reg [31 : 0] mem_read_data1;
reg ready_reg; reg ready_reg;
wire fw_app_cs; wire fw_app_cs;
reg bank0; reg bank0;
reg bank1; reg bank1;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -51,99 +51,97 @@ module fw_ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Block RAM instances. // Block RAM instances.
//---------------------------------------------------------------- //----------------------------------------------------------------
SB_RAM40_4K fw_ram0_0( SB_RAM40_4K fw_ram0_0 (
.RDATA(mem_read_data0[15 : 0]), .RDATA(mem_read_data0[15 : 0]),
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank0), .RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[15 : 0]), .WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank0)), .WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[1]}}, {8{~we[0]}}}) .MASK({{8{~we[1]}}, {8{~we[0]}}})
); );
SB_RAM40_4K fw_ram0_1( SB_RAM40_4K fw_ram0_1 (
.RDATA(mem_read_data0[31 : 16]), .RDATA(mem_read_data0[31 : 16]),
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank0), .RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[31 : 16]), .WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank0)), .WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[3]}}, {8{~we[2]}}}) .MASK({{8{~we[3]}}, {8{~we[2]}}})
); );
SB_RAM40_4K fw_ram1_0( SB_RAM40_4K fw_ram1_0 (
.RDATA(mem_read_data1[15 : 0]), .RDATA(mem_read_data1[15 : 0]),
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank1), .RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[15 : 0]), .WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank1)), .WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[1]}}, {8{~we[0]}}}) .MASK({{8{~we[1]}}, {8{~we[0]}}})
); );
SB_RAM40_4K fw_ram1_1( SB_RAM40_4K fw_ram1_1 (
.RDATA(mem_read_data1[31 : 16]), .RDATA(mem_read_data1[31 : 16]),
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank1), .RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[31 : 16]), .WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank1)), .WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[3]}}, {8{~we[2]}}}) .MASK({{8{~we[3]}}, {8{~we[2]}}})
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin ready_reg <= 1'h0;
ready_reg <= 1'h0;
end
else begin
ready_reg <= cs;
end
end end
else begin
ready_reg <= cs;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// rw_mux // rw_mux
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rw_mux
begin : rw_mux; bank0 = 1'h0;
bank0 = 1'h0; bank1 = 1'h0;
bank1 = 1'h0; tmp_read_data = 32'h0;
tmp_read_data = 32'h0;
if (fw_app_cs) begin if (fw_app_cs) begin
if (address[8]) begin if (address[8]) begin
bank1 = 1'h1; bank1 = 1'h1;
tmp_read_data = mem_read_data1; tmp_read_data = mem_read_data1;
end end
else begin else begin
bank0 = 1'h1; bank0 = 1'h1;
tmp_read_data = mem_read_data0; tmp_read_data = mem_read_data0;
end
end end
end end
end
endmodule // fw_ram endmodule // fw_ram
//====================================================================== //======================================================================
// EOF fw_ram.v // EOF fw_ram.v

166
hw/application_fpga/core/ram/rtl/ram.v
View File

@ -18,20 +18,20 @@
`default_nettype none `default_nettype none
module ram( module ram (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire [14 : 0] ram_addr_rand, input wire [14 : 0] ram_addr_rand,
input wire [31 : 0] ram_data_rand, input wire [31 : 0] ram_data_rand,
input wire cs, input wire cs,
input wire [03 : 0] we, input wire [ 3 : 0] we,
input wire [15 : 0] address, input wire [15 : 0] address,
input wire [31 : 0] write_data, input wire [31 : 0] write_data,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -60,58 +60,58 @@ module ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
// SPRAM instances. // SPRAM instances.
//---------------------------------------------------------------- //----------------------------------------------------------------
SB_SPRAM256KA spram0( SB_SPRAM256KA spram0 (
.ADDRESS(scrambled_ram_addr[13:0]), .ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[15:0]), .DATAIN(scrambled_write_data[15:0]),
.MASKWREN({we[1], we[1], we[0], we[0]}), .MASKWREN({we[1], we[1], we[0], we[0]}),
.WREN(we[1] | we[0]), .WREN(we[1] | we[0]),
.CHIPSELECT(cs0), .CHIPSELECT(cs0),
.CLOCK(clk), .CLOCK(clk),
.STANDBY(1'b0), .STANDBY(1'b0),
.SLEEP(1'b0), .SLEEP(1'b0),
.POWEROFF(1'b1), .POWEROFF(1'b1),
.DATAOUT(read_data0[15:0]) .DATAOUT(read_data0[15:0])
); );
SB_SPRAM256KA spram1( SB_SPRAM256KA spram1 (
.ADDRESS(scrambled_ram_addr[13:0]), .ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[31:16]), .DATAIN(scrambled_write_data[31:16]),
.MASKWREN({we[3], we[3], we[2], we[2]}), .MASKWREN({we[3], we[3], we[2], we[2]}),
.WREN(we[3] | we[2]), .WREN(we[3] | we[2]),
.CHIPSELECT(cs0), .CHIPSELECT(cs0),
.CLOCK(clk), .CLOCK(clk),
.STANDBY(1'b0), .STANDBY(1'b0),
.SLEEP(1'b0), .SLEEP(1'b0),
.POWEROFF(1'b1), .POWEROFF(1'b1),
.DATAOUT(read_data0[31:16]) .DATAOUT(read_data0[31:16])
); );
SB_SPRAM256KA spram2( SB_SPRAM256KA spram2 (
.ADDRESS(scrambled_ram_addr[13:0]), .ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[15:0]), .DATAIN(scrambled_write_data[15:0]),
.MASKWREN({we[1], we[1], we[0], we[0]}), .MASKWREN({we[1], we[1], we[0], we[0]}),
.WREN(we[1] | we[0]), .WREN(we[1] | we[0]),
.CHIPSELECT(cs1), .CHIPSELECT(cs1),
.CLOCK(clk), .CLOCK(clk),
.STANDBY(1'b0), .STANDBY(1'b0),
.SLEEP(1'b0), .SLEEP(1'b0),
.POWEROFF(1'b1), .POWEROFF(1'b1),
.DATAOUT(read_data1[15:0]) .DATAOUT(read_data1[15:0])
); );
SB_SPRAM256KA spram3( SB_SPRAM256KA spram3 (
.ADDRESS(scrambled_ram_addr[13:0]), .ADDRESS(scrambled_ram_addr[13:0]),
.DATAIN(scrambled_write_data[31:16]), .DATAIN(scrambled_write_data[31:16]),
.MASKWREN({we[3], we[3], we[2], we[2]}), .MASKWREN({we[3], we[3], we[2], we[2]}),
.WREN(we[3] | we[2]), .WREN(we[3] | we[2]),
.CHIPSELECT(cs1), .CHIPSELECT(cs1),
.CLOCK(clk), .CLOCK(clk),
.STANDBY(1'b0), .STANDBY(1'b0),
.SLEEP(1'b0), .SLEEP(1'b0),
.POWEROFF(1'b1), .POWEROFF(1'b1),
.DATAOUT(read_data1[31:16]) .DATAOUT(read_data1[31:16])
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -121,15 +121,14 @@ module ram(
// This simply creates a one cycle access latency to match // This simply creates a one cycle access latency to match
// the latency of the spram blocks. // the latency of the spram blocks.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin ready_reg <= 1'h0;
ready_reg <= 1'h0;
end
else begin
ready_reg <= cs;
end
end end
else begin
ready_reg <= cs;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -138,12 +137,11 @@ module ram(
// Scramble address and write data, and descramble read data using // Scramble address and write data, and descramble read data using
// the ram_addr_rand and ram_data_rand seeds. // the ram_addr_rand and ram_data_rand seeds.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : scramble_descramble
begin: scramble_descramble scrambled_ram_addr = address[14 : 0] ^ ram_addr_rand;
scrambled_ram_addr = address[14 : 0] ^ ram_addr_rand; scrambled_write_data = write_data ^ ram_data_rand ^ {2{address}};
scrambled_write_data = write_data ^ ram_data_rand ^ {2{address}}; descrambled_read_data = muxed_read_data ^ ram_data_rand ^ {2{address}};
descrambled_read_data = muxed_read_data ^ ram_data_rand ^ {2{address}}; end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -152,19 +150,19 @@ module ram(
// Select which of the data read from the banks should be // Select which of the data read from the banks should be
// returned during a read access. // returned during a read access.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : mem_mux
begin : mem_mux cs0 = ~scrambled_ram_addr[14] & cs;
cs0 = ~scrambled_ram_addr[14] & cs; cs1 = scrambled_ram_addr[14] & cs;
cs1 = scrambled_ram_addr[14] & cs;
if (scrambled_ram_addr[14]) begin if (scrambled_ram_addr[14]) begin
muxed_read_data = read_data1; muxed_read_data = read_data1;
end else begin
muxed_read_data = read_data0;
end
end end
else begin
muxed_read_data = read_data0;
end
end
endmodule // ram endmodule // ram
//====================================================================== //======================================================================
// EOF ram.v // EOF ram.v

52
hw/application_fpga/core/rom/rtl/rom.v
View File

@ -14,17 +14,17 @@
`default_nettype none `default_nettype none
module rom( module rom (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire cs, input wire cs,
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
input wire [11 : 0] address, input wire [11 : 0] address,
/* verilator lint_on UNUSED */ /* verilator lint_on UNUSED */
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -41,7 +41,7 @@ module rom(
// Max size for the ROM is 3072 words, and the address is // Max size for the ROM is 3072 words, and the address is
// 12 bits to support ROM with this number of words. // 12 bits to support ROM with this number of words.
localparam EBR_MEM_SIZE = `BRAM_FW_SIZE; localparam EBR_MEM_SIZE = `BRAM_FW_SIZE;
reg [31 : 0] memory [0 : (EBR_MEM_SIZE - 1)]; reg [31 : 0] memory[0 : (EBR_MEM_SIZE - 1)];
initial $readmemh(`FIRMWARE_HEX, memory); initial $readmemh(`FIRMWARE_HEX, memory);
reg [31 : 0] rom_rdata; reg [31 : 0] rom_rdata;
@ -58,28 +58,26 @@ module rom(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin ready_reg <= 1'h0;
ready_reg <= 1'h0; end
end else begin
else begin ready_reg <= cs;
ready_reg <= cs; end
end end // reg_update
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
// rom_logic // rom_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rom_logic
begin : rom_logic /* verilator lint_off WIDTH */
/* verilator lint_off WIDTH */ rom_rdata = memory[address];
rom_rdata = memory[address]; /* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */ end
end
endmodule // rom endmodule // rom
//====================================================================== //======================================================================
// EOF rom..v // EOF rom..v

192
hw/application_fpga/core/timer/rtl/timer.v
View File

@ -13,54 +13,54 @@
`default_nettype none `default_nettype none
module timer( module timer (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire cs, input wire cs,
input wire we, input wire we,
input wire [7 : 0] address, input wire [ 7 : 0] address,
input wire [31 : 0] write_data, input wire [31 : 0] write_data,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_CTRL = 8'h08; localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0; localparam CTRL_START_BIT = 0;
localparam CTRL_STOP_BIT = 1; localparam CTRL_STOP_BIT = 1;
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_RUNNING_BIT = 0; localparam STATUS_RUNNING_BIT = 0;
localparam ADDR_PRESCALER = 8'h0a; localparam ADDR_PRESCALER = 8'h0a;
localparam ADDR_TIMER = 8'h0b; localparam ADDR_TIMER = 8'h0b;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] prescaler_reg; reg [31 : 0] prescaler_reg;
reg prescaler_we; reg prescaler_we;
reg [31 : 0] timer_reg; reg [31 : 0] timer_reg;
reg timer_we; reg timer_we;
reg start_reg; reg start_reg;
reg start_new; reg start_new;
reg stop_reg; reg stop_reg;
reg stop_new; reg stop_new;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] tmp_read_data; reg [31 : 0] tmp_read_data;
reg tmp_ready; reg tmp_ready;
wire core_running; wire core_running;
@ -77,44 +77,43 @@ module timer(
//---------------------------------------------------------------- //----------------------------------------------------------------
// core instantiation. // core instantiation.
//---------------------------------------------------------------- //----------------------------------------------------------------
timer_core core( timer_core core (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.prescaler_init(prescaler_reg), .prescaler_init(prescaler_reg),
.timer_init(timer_reg), .timer_init(timer_reg),
.start(start_reg), .start(start_reg),
.stop(stop_reg), .stop(stop_reg),
.curr_timer(core_curr_timer), .curr_timer(core_curr_timer),
.running(core_running) .running(core_running)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin start_reg <= 1'h0;
start_reg <= 1'h0; stop_reg <= 1'h0;
stop_reg <= 1'h0; prescaler_reg <= 32'h0;
prescaler_reg <= 32'h0; timer_reg <= 32'h0;
timer_reg <= 32'h0; end
end else begin
else begin start_reg <= start_new;
start_reg <= start_new; stop_reg <= stop_new;
stop_reg <= stop_new;
if (prescaler_we) begin if (prescaler_we) begin
prescaler_reg <= write_data; prescaler_reg <= write_data;
end
if (timer_we) begin
timer_reg <= write_data;
end
end end
end // reg_update
if (timer_we) begin
timer_reg <= write_data;
end
end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -122,56 +121,55 @@ module timer(
// //
// The interface command decoding logic. // The interface command decoding logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api start_new = 1'h0;
start_new = 1'h0; stop_new = 1'h0;
stop_new = 1'h0; prescaler_we = 1'h0;
prescaler_we = 1'h0; timer_we = 1'h0;
timer_we = 1'h0; tmp_read_data = 32'h0;
tmp_read_data = 32'h0; tmp_ready = 1'h0;
tmp_ready = 1'h0;
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (we) begin if (we) begin
if (address == ADDR_CTRL) begin if (address == ADDR_CTRL) begin
start_new = write_data[CTRL_START_BIT]; start_new = write_data[CTRL_START_BIT];
stop_new = write_data[CTRL_STOP_BIT]; stop_new = write_data[CTRL_STOP_BIT];
end
if (!core_running) begin
if (address == ADDR_PRESCALER) begin
prescaler_we = 1'h1;
end
if (address == ADDR_TIMER) begin
timer_we = 1'h1;
end
end
end end
else begin if (!core_running) begin
if (address == ADDR_STATUS) begin if (address == ADDR_PRESCALER) begin
tmp_read_data[STATUS_RUNNING_BIT] = core_running; prescaler_we = 1'h1;
end end
if (address == ADDR_PRESCALER) begin if (address == ADDR_TIMER) begin
tmp_read_data = prescaler_reg; timer_we = 1'h1;
end end
if (address == ADDR_TIMER) begin
if (!core_running) begin
tmp_read_data = timer_reg;
end
else begin
tmp_read_data = core_curr_timer;
end
end
end end
end end
end // addr_decoder
endmodule // timer else begin
if (address == ADDR_STATUS) begin
tmp_read_data[STATUS_RUNNING_BIT] = core_running;
end
if (address == ADDR_PRESCALER) begin
tmp_read_data = prescaler_reg;
end
if (address == ADDR_TIMER) begin
if (!core_running) begin
tmp_read_data = timer_reg;
end
else begin
tmp_read_data = core_curr_timer;
end
end
end
end
end // addr_decoder
endmodule // timer
//====================================================================== //======================================================================
// EOF timer.v // EOF timer.v

276
hw/application_fpga/core/timer/rtl/timer_core.v
View File

@ -13,26 +13,26 @@
`default_nettype none `default_nettype none
module timer_core( module timer_core (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire [31 : 0] prescaler_init, input wire [31 : 0] prescaler_init,
input wire [31 : 0] timer_init, input wire [31 : 0] timer_init,
input wire start, input wire start,
input wire stop, input wire stop,
output wire [31 : 0] curr_timer, output wire [31 : 0] curr_timer,
output wire running output wire running
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam CTRL_IDLE = 2'h0; localparam CTRL_IDLE = 2'h0;
localparam CTRL_PRESCALER = 2'h1; localparam CTRL_PRESCALER = 2'h1;
localparam CTRL_TIMER = 2'h2; localparam CTRL_TIMER = 2'h2;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -54,8 +54,8 @@ module timer_core(
reg timer_set; reg timer_set;
reg timer_dec; reg timer_dec;
reg [1 : 0] core_ctrl_reg; reg [ 1 : 0] core_ctrl_reg;
reg [1 : 0] core_ctrl_new; reg [ 1 : 0] core_ctrl_new;
reg core_ctrl_we; reg core_ctrl_we;
@ -69,164 +69,158 @@ module timer_core(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update if (!reset_n) begin
if (!reset_n) running_reg <= 1'h0;
begin prescaler_reg <= 32'h0;
running_reg <= 1'h0; timer_reg <= 32'h0;
prescaler_reg <= 32'h0; core_ctrl_reg <= CTRL_IDLE;
timer_reg <= 32'h0; end
core_ctrl_reg <= CTRL_IDLE; else begin
end if (running_we) begin
else running_reg <= running_new;
begin end
if (running_we) begin
running_reg <= running_new;
end
if (prescaler_we) begin if (prescaler_we) begin
prescaler_reg <= prescaler_new; prescaler_reg <= prescaler_new;
end end
if (timer_we) begin if (timer_we) begin
timer_reg <= timer_new; timer_reg <= timer_new;
end end
if (core_ctrl_we) begin if (core_ctrl_we) begin
core_ctrl_reg <= core_ctrl_new; core_ctrl_reg <= core_ctrl_new;
end end
end end
end // reg_update end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
// prescaler_ctr // prescaler_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : prescaler_ctr
begin : prescaler_ctr prescaler_new = 32'h0;
prescaler_new = 32'h0; prescaler_we = 1'h0;
prescaler_we = 1'h0;
if (prescaler_set) begin if (prescaler_set) begin
prescaler_new = prescaler_init; prescaler_new = prescaler_init;
prescaler_we = 1'h1; prescaler_we = 1'h1;
end
else if (prescaler_dec) begin
prescaler_new = prescaler_reg - 1'h1;
prescaler_we = 1'h1;
end
end end
else if (prescaler_dec) begin
prescaler_new = prescaler_reg - 1'h1;
prescaler_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// timer_ctr // timer_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : timer_ctr
begin : timer_ctr timer_new = 32'h0;
timer_new = 32'h0; timer_we = 1'h0;
timer_we = 1'h0;
if (timer_set) begin if (timer_set) begin
timer_new = timer_init; timer_new = timer_init;
timer_we = 1'h1; timer_we = 1'h1;
end
else if (timer_dec) begin
timer_new = timer_reg - 1'h1;
timer_we = 1'h1;
end
end end
else if (timer_dec) begin
timer_new = timer_reg - 1'h1;
timer_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// Core control FSM. // Core control FSM.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : core_ctrl
begin : core_ctrl running_new = 1'h0;
running_new = 1'h0; running_we = 1'h0;
running_we = 1'h0; prescaler_set = 1'h0;
prescaler_set = 1'h0; prescaler_dec = 1'h0;
prescaler_dec = 1'h0; timer_set = 1'h0;
timer_set = 1'h0; timer_dec = 1'h0;
timer_dec = 1'h0; core_ctrl_new = CTRL_IDLE;
core_ctrl_new = CTRL_IDLE; core_ctrl_we = 1'h0;
core_ctrl_we = 1'h0;
case (core_ctrl_reg) case (core_ctrl_reg)
CTRL_IDLE: begin CTRL_IDLE: begin
if (start) begin if (start) begin
running_new = 1'h1; running_new = 1'h1;
running_we = 1'h1; running_we = 1'h1;
prescaler_set = 1'h1; prescaler_set = 1'h1;
timer_set = 1'h1; timer_set = 1'h1;
if (prescaler_init == 0) begin if (prescaler_init == 0) begin
core_ctrl_new = CTRL_TIMER; core_ctrl_new = CTRL_TIMER;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end end
else begin else begin
core_ctrl_new = CTRL_PRESCALER; core_ctrl_new = CTRL_PRESCALER;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end
end end
end end
end
CTRL_PRESCALER: begin CTRL_PRESCALER: begin
if (stop) begin if (stop) begin
running_new = 1'h0; running_new = 1'h0;
running_we = 1'h1; running_we = 1'h1;
core_ctrl_new = CTRL_IDLE; core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1; core_ctrl_we = 1'h1;
end
else begin
if (prescaler_reg == 1) begin
core_ctrl_new = CTRL_TIMER;
core_ctrl_we = 1'h1;
end
else begin
prescaler_dec = 1'h1;
end
end
end
CTRL_TIMER: begin
if (stop) begin
running_new = 1'h0;
running_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1;
end
else begin
if (timer_reg == 1) begin
running_new = 1'h0;
running_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1;
end
else begin
timer_dec = 1'h1;
if (prescaler_init > 0) begin
prescaler_set = 1'h1;
core_ctrl_new = CTRL_PRESCALER;
core_ctrl_we = 1'h1;
end
end
end
end
default: begin
end end
endcase // case (core_ctrl_reg)
end // core_ctrl
endmodule // timer_core else begin
if (prescaler_reg == 1) begin
core_ctrl_new = CTRL_TIMER;
core_ctrl_we = 1'h1;
end
else begin
prescaler_dec = 1'h1;
end
end
end
CTRL_TIMER: begin
if (stop) begin
running_new = 1'h0;
running_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1;
end
else begin
if (timer_reg == 1) begin
running_new = 1'h0;
running_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
core_ctrl_we = 1'h1;
end
else begin
timer_dec = 1'h1;
if (prescaler_init > 0) begin
prescaler_set = 1'h1;
core_ctrl_new = CTRL_PRESCALER;
core_ctrl_we = 1'h1;
end
end
end
end
default: begin
end
endcase // case (core_ctrl_reg)
end // core_ctrl
endmodule // timer_core
//====================================================================== //======================================================================
// EOF timer_core.v // EOF timer_core.v

182
hw/application_fpga/core/timer/tb/tb_timer.v
View File

@ -13,63 +13,63 @@
`default_nettype none `default_nettype none
module tb_timer(); module tb_timer ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 0; parameter DEBUG = 0;
parameter DUMP_WAIT = 0; parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_CTRL = 8'h08; localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0; localparam CTRL_START_BIT = 0;
localparam CTRL_STOP_BIT = 1; localparam CTRL_STOP_BIT = 1;
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_RUNNING_BIT = 0; localparam STATUS_RUNNING_BIT = 0;
localparam ADDR_PRESCALER = 8'h0a; localparam ADDR_PRESCALER = 8'h0a;
localparam ADDR_TIMER = 8'h0b; localparam ADDR_TIMER = 8'h0b;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_monitor; reg tb_monitor;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_cs; reg tb_cs;
reg tb_we; reg tb_we;
reg [7 : 0] tb_address; reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data; reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
wire tb_ready; wire tb_ready;
reg [31 : 0] read_data; reg [31 : 0] read_data;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
timer dut( timer dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.cs(tb_cs), .cs(tb_cs),
.we(tb_we), .we(tb_we),
.address(tb_address), .address(tb_address),
.write_data(tb_write_data), .write_data(tb_write_data),
.read_data(tb_read_data), .read_data(tb_read_data),
.ready(tb_ready) .ready(tb_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -77,11 +77,10 @@ module tb_timer();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -90,15 +89,13 @@ module tb_timer();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (tb_monitor) begin
if (tb_monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -113,17 +110,19 @@ module tb_timer();
$display("Cycle: %08d", cycle_ctr); $display("Cycle: %08d", cycle_ctr);
$display(""); $display("");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("cs: 0x%1x, we: 0x%1x, address: 0x%02x, write_data: 0x%08x, read_data: 0x%08x, ready: 0x%1x", $display(
tb_cs, tb_we, tb_address, tb_write_data, tb_read_data, tb_ready); "cs: 0x%1x, we: 0x%1x, address: 0x%02x, write_data: 0x%08x, read_data: 0x%08x, ready: 0x%1x",
tb_cs, tb_we, tb_address, tb_write_data, tb_read_data, tb_ready);
$display(""); $display("");
$display("Internal state:"); $display("Internal state:");
$display("prescaler_reg: 0x%08x, timer_reg: 0x%08x", dut.prescaler_reg, dut.timer_reg); $display("prescaler_reg: 0x%08x, timer_reg: 0x%08x", dut.prescaler_reg, dut.timer_reg);
$display("start_reg: 0x%1x, stop_reg: 0x%1x", dut.start_reg, dut.stop_reg); $display("start_reg: 0x%1x, stop_reg: 0x%1x", dut.start_reg, dut.stop_reg);
$display("core_running: 0x%1x, core_curr_timer: 0x%08x", dut.core_running, dut.core_curr_timer); $display("core_running: 0x%1x, core_curr_timer: 0x%08x", dut.core_running,
dut.core_curr_timer);
$display(""); $display("");
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -138,7 +137,7 @@ module tb_timer();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -148,17 +147,15 @@ module tb_timer();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("--- All %02d test cases completed successfully", tc_ctr);
$display("--- All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("--- %02d tests completed - %02d test cases did not complete successfully.",
begin tc_ctr, error_ctr);
$display("--- %02d tests completed - %02d test cases did not complete successfully.", end
tc_ctr, error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -169,10 +166,10 @@ module tb_timer();
//---------------------------------------------------------------- //----------------------------------------------------------------
task init_sim; task init_sim;
begin begin
cycle_ctr = 0; cycle_ctr = 0;
error_ctr = 0; error_ctr = 0;
tc_ctr = 0; tc_ctr = 0;
tb_monitor = 0; tb_monitor = 0;
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
@ -181,7 +178,7 @@ module tb_timer();
tb_address = 8'h0; tb_address = 8'h0;
tb_write_data = 32'h0; tb_write_data = 32'h0;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -189,14 +186,12 @@ module tb_timer();
// //
// Write the given word to the DUT using the DUT interface. // Write the given word to the DUT using the DUT interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
task write_word(input [11 : 0] address, task write_word(input [11 : 0] address, input [31 : 0] word);
input [31 : 0] word);
begin begin
if (DEBUG) if (DEBUG) begin
begin $display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("");
$display(""); end
end
tb_address = address; tb_address = address;
tb_write_data = word; tb_write_data = word;
@ -206,7 +201,7 @@ module tb_timer();
tb_cs = 0; tb_cs = 0;
tb_we = 0; tb_we = 0;
end end
endtask // write_word endtask // write_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -216,7 +211,7 @@ module tb_timer();
// the word read will be available in the global variable // the word read will be available in the global variable
// read_data. // read_data.
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_word(input [11 : 0] address); task read_word(input [11 : 0] address);
begin begin
tb_address = address; tb_address = address;
tb_cs = 1; tb_cs = 1;
@ -225,13 +220,12 @@ module tb_timer();
read_data = tb_read_data; read_data = tb_read_data;
tb_cs = 0; tb_cs = 0;
if (DEBUG) if (DEBUG) begin
begin $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("");
$display(""); end
end
end end
endtask // read_word endtask // read_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -242,10 +236,9 @@ module tb_timer();
task wait_ready; task wait_ready;
begin : wready begin : wready
read_word(ADDR_STATUS); read_word(ADDR_STATUS);
while (read_data == 0) while (read_data == 0) read_word(ADDR_STATUS);
read_word(ADDR_STATUS);
end end
endtask // wait_ready endtask // wait_ready
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -273,7 +266,7 @@ module tb_timer();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
read_word(ADDR_STATUS); read_word(ADDR_STATUS);
while (read_data) begin while (read_data) begin
read_word(ADDR_STATUS); read_word(ADDR_STATUS);
end end
time_stop = cycle_ctr; time_stop = cycle_ctr;
@ -286,31 +279,30 @@ module tb_timer();
$display("--- test1: completed."); $display("--- test1: completed.");
$display(""); $display("");
end end
endtask // tes1 endtask // tes1
//---------------------------------------------------------------- //----------------------------------------------------------------
// timer_test // timer_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : timer_test
begin : timer_test $display("");
$display(""); $display(" -= Testbench for timer started =-");
$display(" -= Testbench for timer started =-"); $display(" =============================");
$display(" ============================="); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); test1();
display_test_result(); display_test_result();
$display(""); $display("");
$display(" -= Testbench for timer completed =-"); $display(" -= Testbench for timer completed =-");
$display(" ==============================="); $display(" ===============================");
$display(""); $display("");
$finish; $finish;
end // timer_test end // timer_test
endmodule // tb_timer endmodule // tb_timer
//====================================================================== //======================================================================
// EOF tb_timer.v // EOF tb_timer.v

121
hw/application_fpga/core/timer/tb/tb_timer_core.v
View File

@ -13,12 +13,12 @@
`default_nettype none `default_nettype none
module tb_timer_core(); module tb_timer_core ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 0; parameter DEBUG = 0;
parameter DUMP_WAIT = 0; parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
@ -28,10 +28,10 @@ module tb_timer_core();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_monitor; reg tb_monitor;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
@ -46,16 +46,16 @@ module tb_timer_core();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
timer_core dut( timer_core dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.prescaler_init(tb_prescaler_init), .prescaler_init(tb_prescaler_init),
.timer_init(tb_timer_init), .timer_init(tb_timer_init),
.start(tb_start), .start(tb_start),
.stop(tb_stop), .stop(tb_stop),
.curr_timer(tb_curr_timer), .curr_timer(tb_curr_timer),
.running(tb_running) .running(tb_running)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -63,11 +63,10 @@ module tb_timer_core();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -76,15 +75,13 @@ module tb_timer_core();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (tb_monitor) begin
if (tb_monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -99,28 +96,23 @@ module tb_timer_core();
$display("Cycle: %08d", cycle_ctr); $display("Cycle: %08d", cycle_ctr);
$display(""); $display("");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("prescaler_init: 0x%08x, timer_init: 0x%08x", $display("prescaler_init: 0x%08x, timer_init: 0x%08x", dut.prescaler_init, dut.timer_init);
dut.prescaler_init, dut.timer_init); $display("start: 0x%1x, stop: 0x%1x, running: 0x%1x", dut.start, dut.stop, dut.running);
$display("start: 0x%1x, stop: 0x%1x, running: 0x%1x",
dut.start, dut.stop, dut.running);
$display(""); $display("");
$display("Internal state:"); $display("Internal state:");
$display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x", $display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x", dut.prescaler_reg,
dut.prescaler_reg, dut.prescaler_new); dut.prescaler_new);
$display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x", $display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x", dut.prescaler_set, dut.prescaler_dec);
dut.prescaler_set, dut.prescaler_dec);
$display(""); $display("");
$display("timer_reg: 0x%08x, timer_new: 0x%08x", $display("timer_reg: 0x%08x, timer_new: 0x%08x", dut.timer_reg, dut.timer_new);
dut.timer_reg, dut.timer_new); $display("timer_set: 0x%1x, timer_dec: 0x%1x", dut.timer_set, dut.timer_dec);
$display("timer_set: 0x%1x, timer_dec: 0x%1x",
dut.timer_set, dut.timer_dec);
$display(""); $display("");
$display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x", $display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x",
dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we); dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
$display(""); $display("");
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -139,7 +131,7 @@ module tb_timer_core();
$display("--- DUT after reset:"); $display("--- DUT after reset:");
dump_dut_state(); dump_dut_state();
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -154,16 +146,14 @@ module tb_timer_core();
task wait_done; task wait_done;
begin begin
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
while (tb_running) while (tb_running) begin
begin #(CLK_PERIOD);
#(CLK_PERIOD); if (DUMP_WAIT) begin
if (DUMP_WAIT) dump_dut_state();
begin
dump_dut_state();
end
end end
end
end end
endtask // wait_ready endtask // wait_ready
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -187,7 +177,7 @@ module tb_timer_core();
tb_prescaler_init = 32'h0; tb_prescaler_init = 32'h0;
tb_timer_init = 32'h0; tb_timer_init = 32'h0;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -212,7 +202,7 @@ module tb_timer_core();
$display("--- test1 completed."); $display("--- test1 completed.");
$display(""); $display("");
end end
endtask // test1 endtask // test1
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -220,21 +210,20 @@ module tb_timer_core();
// //
// Test vectors from: // Test vectors from:
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : timer_core_test
begin : timer_core_test $display("--- Simulation of timer core started.");
$display("--- Simulation of timer core started."); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); test1();
$display(""); $display("");
$display("--- Simulation of timer core completed."); $display("--- Simulation of timer core completed.");
$finish; $finish;
end // timer_core_test end // timer_core_test
endmodule // tb_timer_core endmodule // tb_timer_core
//====================================================================== //======================================================================
// EOF tb_timer_core.v // EOF tb_timer_core.v

898
hw/application_fpga/core/tk1/rtl/tk1.v
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File diff suppressed because it is too large Load Diff

359
hw/application_fpga/core/tk1/rtl/tk1_spi_master.v
View File

@ -23,68 +23,68 @@
`default_nettype none `default_nettype none
module tk1_spi_master( module tk1_spi_master (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
output wire spi_ss, output wire spi_ss,
output wire spi_sck, output wire spi_sck,
output wire spi_mosi, output wire spi_mosi,
input wire spi_miso, input wire spi_miso,
input wire spi_enable, input wire spi_enable,
input wire spi_enable_vld, input wire spi_enable_vld,
input wire spi_start, input wire spi_start,
input wire [7 : 0] spi_tx_data, input wire [7 : 0] spi_tx_data,
input wire spi_tx_data_vld, input wire spi_tx_data_vld,
output wire [7 : 0] spi_rx_data, output wire [7 : 0] spi_rx_data,
output wire spi_ready output wire spi_ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam CTRL_IDLE = 3'h0; localparam CTRL_IDLE = 3'h0;
localparam CTRL_POS_FLANK = 3'h1; localparam CTRL_POS_FLANK = 3'h1;
localparam CTRL_NEG_FLANK = 3'h2; localparam CTRL_NEG_FLANK = 3'h2;
localparam CTRL_NEXT = 3'h3; localparam CTRL_NEXT = 3'h3;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg spi_ss_reg; reg spi_ss_reg;
reg spi_csk_reg; reg spi_csk_reg;
reg spi_csk_new; reg spi_csk_new;
reg spi_csk_we; reg spi_csk_we;
reg [7 : 0] spi_tx_data_reg; reg [7 : 0] spi_tx_data_reg;
reg [7 : 0] spi_tx_data_new; reg [7 : 0] spi_tx_data_new;
reg spi_tx_data_nxt; reg spi_tx_data_nxt;
reg spi_tx_data_we; reg spi_tx_data_we;
reg [7 : 0] spi_rx_data_reg; reg [7 : 0] spi_rx_data_reg;
reg [7 : 0] spi_rx_data_new; reg [7 : 0] spi_rx_data_new;
reg spi_rx_data_nxt; reg spi_rx_data_nxt;
reg spi_rx_data_we; reg spi_rx_data_we;
reg spi_miso_sample_reg; reg spi_miso_sample_reg;
reg [2 : 0] spi_bit_ctr_reg; reg [2 : 0] spi_bit_ctr_reg;
reg [2 : 0] spi_bit_ctr_new; reg [2 : 0] spi_bit_ctr_new;
reg spi_bit_ctr_rst; reg spi_bit_ctr_rst;
reg spi_bit_ctr_inc; reg spi_bit_ctr_inc;
reg spi_bit_ctr_we; reg spi_bit_ctr_we;
reg spi_ready_reg; reg spi_ready_reg;
reg spi_ready_new; reg spi_ready_new;
reg spi_ready_we; reg spi_ready_we;
reg [2 : 0] spi_ctrl_reg; reg [2 : 0] spi_ctrl_reg;
reg [2 : 0] spi_ctrl_new; reg [2 : 0] spi_ctrl_new;
reg spi_ctrl_we; reg spi_ctrl_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -100,72 +100,70 @@ module tk1_spi_master(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin spi_ss_reg <= 1'h1;
spi_ss_reg <= 1'h1; spi_csk_reg <= 1'h0;
spi_csk_reg <= 1'h0; spi_miso_sample_reg <= 1'h0;
spi_miso_sample_reg <= 1'h0; spi_tx_data_reg <= 8'h0;
spi_tx_data_reg <= 8'h0; spi_rx_data_reg <= 8'h0;
spi_rx_data_reg <= 8'h0; spi_bit_ctr_reg <= 3'h0;
spi_bit_ctr_reg <= 3'h0; spi_ready_reg <= 1'h1;
spi_ready_reg <= 1'h1; spi_ctrl_reg <= CTRL_IDLE;
spi_ctrl_reg <= CTRL_IDLE; end
else begin
spi_miso_sample_reg <= spi_miso;
if (spi_enable_vld) begin
spi_ss_reg <= ~spi_enable;
end end
else begin if (spi_csk_we) begin
spi_miso_sample_reg <= spi_miso; spi_csk_reg <= spi_csk_new;
if (spi_enable_vld) begin
spi_ss_reg <= ~spi_enable;
end
if (spi_csk_we) begin
spi_csk_reg <= spi_csk_new;
end
if (spi_tx_data_we) begin
spi_tx_data_reg <= spi_tx_data_new;
end
if (spi_rx_data_we) begin
spi_rx_data_reg <= spi_rx_data_new;
end
if (spi_ready_we) begin
spi_ready_reg <= spi_ready_new;
end
if (spi_bit_ctr_we) begin
spi_bit_ctr_reg <= spi_bit_ctr_new;
end
if (spi_ctrl_we) begin
spi_ctrl_reg <= spi_ctrl_new;
end
end end
end // reg_update
if (spi_tx_data_we) begin
spi_tx_data_reg <= spi_tx_data_new;
end
if (spi_rx_data_we) begin
spi_rx_data_reg <= spi_rx_data_new;
end
if (spi_ready_we) begin
spi_ready_reg <= spi_ready_new;
end
if (spi_bit_ctr_we) begin
spi_bit_ctr_reg <= spi_bit_ctr_new;
end
if (spi_ctrl_we) begin
spi_ctrl_reg <= spi_ctrl_new;
end
end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
// bit_ctr // bit_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : bit_ctr
begin : bit_ctr spi_bit_ctr_new = 3'h0;
spi_bit_ctr_we = 1'h0;
if (spi_bit_ctr_rst) begin
spi_bit_ctr_new = 3'h0; spi_bit_ctr_new = 3'h0;
spi_bit_ctr_we = 1'h0; spi_bit_ctr_we = 1'h1;
if (spi_bit_ctr_rst) begin
spi_bit_ctr_new = 3'h0;
spi_bit_ctr_we = 1'h1;
end
else if (spi_bit_ctr_inc) begin
spi_bit_ctr_new = spi_bit_ctr_reg + 1'h1;
spi_bit_ctr_we = 1'h1;
end
end end
else if (spi_bit_ctr_inc) begin
spi_bit_ctr_new = spi_bit_ctr_reg + 1'h1;
spi_bit_ctr_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// spi_tx_data_logic // spi_tx_data_logic
@ -173,111 +171,108 @@ module tk1_spi_master(
// Logic for the tx_data shift register. // Logic for the tx_data shift register.
// Either load or shift the data register. // Either load or shift the data register.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : spi_tx_data_logic
begin : spi_tx_data_logic spi_tx_data_new = 8'h0;
spi_tx_data_new = 8'h0; spi_tx_data_we = 1'h0;
spi_tx_data_we = 1'h0;
if (spi_tx_data_vld) begin if (spi_tx_data_vld) begin
if (spi_ready_reg) begin if (spi_ready_reg) begin
spi_tx_data_new = spi_tx_data; spi_tx_data_new = spi_tx_data;
spi_tx_data_we = 1'h1; spi_tx_data_we = 1'h1;
end
end
if (spi_tx_data_nxt) begin
spi_tx_data_new = {spi_tx_data_reg[6 : 0], 1'h0};
spi_tx_data_we = 1'h1;
end end
end end
if (spi_tx_data_nxt) begin
spi_tx_data_new = {spi_tx_data_reg[6 : 0], 1'h0};
spi_tx_data_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// spi_rx_data_logic // spi_rx_data_logic
// Logic for the rx_data shift register. // Logic for the rx_data shift register.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : spi_rx_data_logic
begin : spi_rx_data_logic spi_rx_data_new = 8'h0;
spi_rx_data_we = 1'h0;
if (spi_ss) begin
spi_rx_data_new = 8'h0; spi_rx_data_new = 8'h0;
spi_rx_data_we = 1'h0; spi_rx_data_we = 1'h1;
if (spi_ss) begin
spi_rx_data_new = 8'h0;
spi_rx_data_we = 1'h1;
end
else if (spi_rx_data_nxt) begin
spi_rx_data_new = {spi_rx_data_reg[6 : 0], spi_miso_sample_reg};
spi_rx_data_we = 1'h1;
end
end end
else if (spi_rx_data_nxt) begin
spi_rx_data_new = {spi_rx_data_reg[6 : 0], spi_miso_sample_reg};
spi_rx_data_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// spi_master_ctrl // spi_master_ctrl
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : spi_master_ctrl
begin : spi_master_ctrl spi_rx_data_nxt = 1'h0;
spi_rx_data_nxt = 1'h0; spi_tx_data_nxt = 1'h0;
spi_tx_data_nxt = 1'h0; spi_csk_new = 1'h0;
spi_csk_new = 1'h0; spi_csk_we = 1'h0;
spi_csk_we = 1'h0; spi_bit_ctr_rst = 1'h0;
spi_bit_ctr_rst = 1'h0; spi_bit_ctr_inc = 1'h0;
spi_bit_ctr_inc = 1'h0; spi_ready_new = 1'h0;
spi_ready_new = 1'h0; spi_ready_we = 1'h0;
spi_ready_we = 1'h0; spi_ctrl_new = CTRL_IDLE;
spi_ctrl_new = CTRL_IDLE; spi_ctrl_we = 1'h0;
spi_ctrl_we = 1'h0;
case (spi_ctrl_reg) case (spi_ctrl_reg)
CTRL_IDLE: begin CTRL_IDLE: begin
if (spi_start) begin if (spi_start) begin
spi_csk_new = 1'h0; spi_csk_new = 1'h0;
spi_csk_we = 1'h1; spi_csk_we = 1'h1;
spi_bit_ctr_rst = 1'h1; spi_bit_ctr_rst = 1'h1;
spi_ready_new = 1'h0; spi_ready_new = 1'h0;
spi_ready_we = 1'h1; spi_ready_we = 1'h1;
spi_ctrl_new = CTRL_POS_FLANK; spi_ctrl_new = CTRL_POS_FLANK;
spi_ctrl_we = 1'h1; spi_ctrl_we = 1'h1;
end
end
CTRL_POS_FLANK: begin
spi_csk_new = 1'h1;
spi_csk_we = 1'h1;
spi_ctrl_new = CTRL_NEG_FLANK;
spi_ctrl_we = 1'h1;
end
CTRL_NEG_FLANK: begin
spi_tx_data_nxt = 1'h1;
spi_csk_new = 1'h0;
spi_csk_we = 1'h1;
spi_ctrl_new = CTRL_NEXT;
spi_ctrl_we = 1'h1;
end
CTRL_NEXT: begin
spi_rx_data_nxt = 1'h1;
if (spi_bit_ctr_reg == 3'h7) begin
spi_ready_new = 1'h1;
spi_ready_we = 1'h1;
spi_ctrl_new = CTRL_IDLE;
spi_ctrl_we = 1'h1;
end
else begin
spi_bit_ctr_inc = 1'h1;
spi_ctrl_new = CTRL_POS_FLANK;
spi_ctrl_we = 1'h1;
end
end
default: begin
end end
endcase // case (spi_ctrl_reg) end
end
endmodule // tk1_spi_master CTRL_POS_FLANK: begin
spi_csk_new = 1'h1;
spi_csk_we = 1'h1;
spi_ctrl_new = CTRL_NEG_FLANK;
spi_ctrl_we = 1'h1;
end
CTRL_NEG_FLANK: begin
spi_tx_data_nxt = 1'h1;
spi_csk_new = 1'h0;
spi_csk_we = 1'h1;
spi_ctrl_new = CTRL_NEXT;
spi_ctrl_we = 1'h1;
end
CTRL_NEXT: begin
spi_rx_data_nxt = 1'h1;
if (spi_bit_ctr_reg == 3'h7) begin
spi_ready_new = 1'h1;
spi_ready_we = 1'h1;
spi_ctrl_new = CTRL_IDLE;
spi_ctrl_we = 1'h1;
end
else begin
spi_bit_ctr_inc = 1'h1;
spi_ctrl_new = CTRL_POS_FLANK;
spi_ctrl_we = 1'h1;
end
end
default: begin
end
endcase // case (spi_ctrl_reg)
end
endmodule // tk1_spi_master
//====================================================================== //======================================================================
// EOF tk1_spi_master.v // EOF tk1_spi_master.v

22
hw/application_fpga/core/tk1/rtl/udi_rom.v
View File

@ -13,22 +13,22 @@
//====================================================================== //======================================================================
module udi_rom ( module udi_rom (
input wire [0:0] addr, input wire [ 0:0] addr,
output wire [31:0] data output wire [31:0] data
); );
generate generate
genvar ii; genvar ii;
/* verilator lint_off PINMISSING */ /* verilator lint_off PINMISSING */
for (ii = 0; ii < 32; ii = ii + 1'b1) for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts
begin: luts
(* udi_rom_idx=ii, keep *) SB_LUT4 #(.LUT_INIT({2'h1}) (* udi_rom_idx=ii, keep *) SB_LUT4 #(
) lut_i ( .LUT_INIT({2'h1})
.I0(addr[0]), ) lut_i (
.O(data[ii]) .I0(addr[0]),
); .O (data[ii])
/* verilator lint_on PINMISSING */ );
end /* verilator lint_on PINMISSING */
end
endgenerate endgenerate
endmodule endmodule

24
hw/application_fpga/core/tk1/tb/sb_rgba_drv.v
View File

@ -16,19 +16,19 @@
`default_nettype none `default_nettype none
module SB_RGBA_DRV ( module SB_RGBA_DRV (
input wire RGBLEDEN, input wire RGBLEDEN,
input wire RGB0PWM, input wire RGB0PWM,
input wire RGB1PWM, input wire RGB1PWM,
input wire RGB2PWM, input wire RGB2PWM,
/* verilator lint_off UNUSEDSIGNAL */ /* verilator lint_off UNUSEDSIGNAL */
input wire CURREN, input wire CURREN,
/* verilator lint_on UNUSEDSIGNAL */ /* verilator lint_on UNUSEDSIGNAL */
output wire RGB0, output wire RGB0,
output wire RGB1, output wire RGB1,
output wire RGB2 output wire RGB2
); );
/* verilator lint_off UNUSEDPARAM */ /* verilator lint_off UNUSEDPARAM */
parameter CURRENT_MODE = 1; parameter CURRENT_MODE = 1;
@ -41,7 +41,7 @@ module SB_RGBA_DRV (
assign RGB1 = RGB1PWM & RGBLEDEN; assign RGB1 = RGB1PWM & RGBLEDEN;
assign RGB2 = RGB2PWM & RGBLEDEN; assign RGB2 = RGB2PWM & RGBLEDEN;
endmodule // SB_RGBA_DRV endmodule // SB_RGBA_DRV
//====================================================================== //======================================================================
// EOF SB_RGBA_DRV.v // EOF SB_RGBA_DRV.v

348
hw/application_fpga/core/tk1/tb/tb_tk1.v
View File

@ -13,62 +13,62 @@
`default_nettype none `default_nettype none
module tb_tk1(); module tb_tk1 ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 1; parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_NAME0 = 8'h00; localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01; localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02; localparam ADDR_VERSION = 8'h02;
localparam ADDR_SWITCH_APP = 8'h08; localparam ADDR_SWITCH_APP = 8'h08;
localparam ADDR_LED = 8'h09; localparam ADDR_LED = 8'h09;
localparam LED_R_BIT = 2; localparam LED_R_BIT = 2;
localparam LED_G_BIT = 1; localparam LED_G_BIT = 1;
localparam LED_B_BIT = 0; localparam LED_B_BIT = 0;
localparam ADDR_GPIO = 8'h0a; localparam ADDR_GPIO = 8'h0a;
localparam GPIO1_BIT = 0; localparam GPIO1_BIT = 0;
localparam GPIO2_BIT = 1; localparam GPIO2_BIT = 1;
localparam GPIO3_BIT = 2; localparam GPIO3_BIT = 2;
localparam GPIO4_BIT = 3; localparam GPIO4_BIT = 3;
localparam ADDR_APP_START = 8'h0c; localparam ADDR_APP_START = 8'h0c;
localparam ADDR_APP_SIZE = 8'h0d; localparam ADDR_APP_SIZE = 8'h0d;
localparam ADDR_BLAKE2S = 8'h10; localparam ADDR_BLAKE2S = 8'h10;
localparam ADDR_CDI_FIRST = 8'h20; localparam ADDR_CDI_FIRST = 8'h20;
localparam ADDR_CDI_LAST = 8'h27; localparam ADDR_CDI_LAST = 8'h27;
localparam ADDR_UDI_FIRST = 8'h30; localparam ADDR_UDI_FIRST = 8'h30;
localparam ADDR_UDI_LAST = 8'h31; localparam ADDR_UDI_LAST = 8'h31;
localparam ADDR_RAM_ADDR_RAND = 8'h40; localparam ADDR_RAM_ADDR_RAND = 8'h40;
localparam ADDR_RAM_DATA_RAND = 8'h41; localparam ADDR_RAM_DATA_RAND = 8'h41;
localparam ADDR_CPU_MON_CTRL = 8'h60; localparam ADDR_CPU_MON_CTRL = 8'h60;
localparam ADDR_CPU_MON_FIRST = 8'h61; localparam ADDR_CPU_MON_FIRST = 8'h61;
localparam ADDR_CPU_MON_LAST = 8'h62; localparam ADDR_CPU_MON_LAST = 8'h62;
localparam ADDR_SPI_EN = 8'h80; localparam ADDR_SPI_EN = 8'h80;
localparam ADDR_SPI_XFER = 8'h81; localparam ADDR_SPI_XFER = 8'h81;
localparam ADDR_SPI_DATA = 8'h82; localparam ADDR_SPI_DATA = 8'h82;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_monitor; reg tb_monitor;
reg tb_main_monitor; reg tb_main_monitor;
reg tb_spi_monitor; reg tb_spi_monitor;
@ -102,7 +102,7 @@ module tb_tk1();
reg tb_cs; reg tb_cs;
reg tb_we; reg tb_we;
reg [7 : 0] tb_address; reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data; reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
wire tb_ready; wire tb_ready;
@ -117,42 +117,42 @@ module tb_tk1();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
tk1 dut( tk1 dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.cpu_trap(tb_cpu_trap), .cpu_trap(tb_cpu_trap),
.fw_app_mode(tb_fw_app_mode), .fw_app_mode(tb_fw_app_mode),
.cpu_addr(tb_cpu_addr), .cpu_addr (tb_cpu_addr),
.cpu_instr(tb_cpu_instr), .cpu_instr (tb_cpu_instr),
.cpu_valid(tb_cpu_valid), .cpu_valid (tb_cpu_valid),
.force_trap(tb_force_trap), .force_trap(tb_force_trap),
.ram_addr_rand(tb_ram_addr_rand), .ram_addr_rand(tb_ram_addr_rand),
.ram_data_rand(tb_ram_data_rand), .ram_data_rand(tb_ram_data_rand),
.led_r(tb_led_r), .led_r(tb_led_r),
.led_g(tb_led_g), .led_g(tb_led_g),
.led_b(tb_led_b), .led_b(tb_led_b),
.gpio1(tb_gpio1), .gpio1(tb_gpio1),
.gpio2(tb_gpio2), .gpio2(tb_gpio2),
.gpio3(tb_gpio3), .gpio3(tb_gpio3),
.gpio4(tb_gpio4), .gpio4(tb_gpio4),
.spi_ss(tb_spi_ss), .spi_ss (tb_spi_ss),
.spi_sck(tb_spi_sck), .spi_sck (tb_spi_sck),
.spi_mosi(tb_spi_mosi), .spi_mosi(tb_spi_mosi),
.spi_miso(tb_spi_miso), .spi_miso(tb_spi_miso),
.cs(tb_cs), .cs(tb_cs),
.we(tb_we), .we(tb_we),
.address(tb_address), .address(tb_address),
.write_data(tb_write_data), .write_data(tb_write_data),
.read_data(tb_read_data), .read_data(tb_read_data),
.ready(tb_ready) .ready(tb_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -160,11 +160,10 @@ module tb_tk1();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -173,15 +172,13 @@ module tb_tk1();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (tb_monitor) begin
if (tb_monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -194,31 +191,33 @@ module tb_tk1();
$display("State of DUT at cycle: %08d", cycle_ctr); $display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------"); $display("------------");
if (tb_main_monitor) begin if (tb_main_monitor) begin
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode); $display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode);
$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x", $display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap); tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand, tb_ram_data_rand); $display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand,
$display("led_r: 0x%1x, led_g: 0x%1x, led_b: 0x%1x", tb_led_r, tb_led_g, tb_led_b); tb_ram_data_rand);
$display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we, tb_address); $display("led_r: 0x%1x, led_g: 0x%1x, led_b: 0x%1x", tb_led_r, tb_led_g, tb_led_b);
$display("write_data: 0x%08x, read_data: 0x%08x", tb_write_data, tb_read_data); $display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we,
$display(""); tb_address);
$display("write_data: 0x%08x, read_data: 0x%08x", tb_write_data, tb_read_data);
$display("");
$display("Internal state:"); $display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data); $display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
$display(""); $display("");
end end
if (tb_spi_monitor) begin if (tb_spi_monitor) begin
$display("SPI I/O and internal state:"); $display("SPI I/O and internal state:");
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso: 0x%1x", $display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso: 0x%1x", tb_spi_ss,
tb_spi_ss, tb_spi_sck, tb_spi_mosi, tb_spi_miso); tb_spi_sck, tb_spi_mosi, tb_spi_miso);
end end
$display(""); $display("");
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -233,7 +232,7 @@ module tb_tk1();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -243,16 +242,14 @@ module tb_tk1();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("--- All %02d test cases completed successfully", tc_ctr);
$display("--- All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("--- %02d tests completed - %02d errors detected.", tc_ctr, error_ctr);
begin end
$display("--- %02d tests completed - %02d errors detected.", tc_ctr, error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -285,7 +282,7 @@ module tb_tk1();
tb_address = 8'h0; tb_address = 8'h0;
tb_write_data = 32'h0; tb_write_data = 32'h0;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -293,14 +290,12 @@ module tb_tk1();
// //
// Write the given word to the DUT using the DUT interface. // Write the given word to the DUT using the DUT interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
task write_word(input [11 : 0] address, task write_word(input [11 : 0] address, input [31 : 0] word);
input [31 : 0] word);
begin begin
if (DEBUG) if (DEBUG) begin
begin $display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("");
$display(""); end
end
tb_address = address; tb_address = address;
tb_write_data = word; tb_write_data = word;
@ -310,7 +305,7 @@ module tb_tk1();
tb_cs = 0; tb_cs = 0;
tb_we = 0; tb_we = 0;
end end
endtask // write_word endtask // write_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -320,7 +315,7 @@ module tb_tk1();
// the word read will be available in the global variable // the word read will be available in the global variable
// tb_read_data. // tb_read_data.
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_word(input [11 : 0] address); task read_word(input [11 : 0] address);
begin : read_word begin : read_word
reg [31 : 0] read_data; reg [31 : 0] read_data;
@ -333,7 +328,7 @@ module tb_tk1();
#(CLK_PERIOD); #(CLK_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
end end
endtask // read_word endtask // read_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -346,7 +341,7 @@ module tb_tk1();
// The function also checks that the data read matches // The function also checks that the data read matches
// the expected value or not. // the expected value or not.
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_check_word(input [11 : 0] address, input [31 : 0] expected); task read_check_word(input [11 : 0] address, input [31 : 0] expected);
begin : read_check_word begin : read_check_word
reg [31 : 0] read_data; reg [31 : 0] read_data;
@ -359,19 +354,19 @@ module tb_tk1();
#(CLK_PERIOD); #(CLK_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
if (DEBUG) if (DEBUG) begin
begin if (read_data == expected) begin
if (read_data == expected) begin $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
read_data, address, expected);
error_ctr = error_ctr + 1;
end
$display("");
end end
else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1;
end
$display("");
end
end end
endtask // read_check_word endtask // read_check_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -392,7 +387,7 @@ module tb_tk1();
$display("--- test1: completed."); $display("--- test1: completed.");
$display(""); $display("");
end end
endtask // test1 endtask // test1
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -407,12 +402,12 @@ module tb_tk1();
$display("--- test2: Read out UDI started."); $display("--- test2: Read out UDI started.");
read_check_word(ADDR_UDI_FIRST, 32'h00010203); read_check_word(ADDR_UDI_FIRST, 32'h00010203);
read_check_word(ADDR_UDI_LAST, 32'h04050607); read_check_word(ADDR_UDI_LAST, 32'h04050607);
$display("--- test2: completed."); $display("--- test2: completed.");
$display(""); $display("");
end end
endtask // test2 endtask // test2
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -443,7 +438,7 @@ module tb_tk1();
read_check_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3); read_check_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3);
read_check_word(ADDR_CDI_FIRST + 5, 32'h90919293); read_check_word(ADDR_CDI_FIRST + 5, 32'h90919293);
read_check_word(ADDR_CDI_FIRST + 6, 32'h80818283); read_check_word(ADDR_CDI_FIRST + 6, 32'h80818283);
read_check_word(ADDR_CDI_LAST + 0, 32'h70717273); read_check_word(ADDR_CDI_LAST + 0, 32'h70717273);
$display("--- test3: Switch to app mode."); $display("--- test3: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hdeadbeef); write_word(ADDR_SWITCH_APP, 32'hdeadbeef);
@ -466,12 +461,12 @@ module tb_tk1();
read_check_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3); read_check_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3);
read_check_word(ADDR_CDI_FIRST + 5, 32'h90919293); read_check_word(ADDR_CDI_FIRST + 5, 32'h90919293);
read_check_word(ADDR_CDI_FIRST + 6, 32'h80818283); read_check_word(ADDR_CDI_FIRST + 6, 32'h80818283);
read_check_word(ADDR_CDI_LAST + 0, 32'h70717273); read_check_word(ADDR_CDI_LAST + 0, 32'h70717273);
$display("--- test3: completed."); $display("--- test3: completed.");
$display(""); $display("");
end end
endtask // test3 endtask // test3
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -505,7 +500,7 @@ module tb_tk1();
$display("--- test4: completed."); $display("--- test4: completed.");
$display(""); $display("");
end end
endtask // test4 endtask // test4
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -543,7 +538,7 @@ module tb_tk1();
$display("--- test5: completed."); $display("--- test5: completed.");
$display(""); $display("");
end end
endtask // test5 endtask // test5
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -563,8 +558,10 @@ module tb_tk1();
write_word(ADDR_RAM_ADDR_RAND, 32'h13371337); write_word(ADDR_RAM_ADDR_RAND, 32'h13371337);
write_word(ADDR_RAM_DATA_RAND, 32'h47114711); write_word(ADDR_RAM_DATA_RAND, 32'h47114711);
$display("--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers."); $display(
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x", dut.ram_addr_rand, dut.ram_data_rand); "--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: Switch to app mode."); $display("--- test6: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hf000000); write_word(ADDR_SWITCH_APP, 32'hf000000);
@ -573,13 +570,15 @@ module tb_tk1();
write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef); write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef);
write_word(ADDR_RAM_DATA_RAND, 32'hf00ff00f); write_word(ADDR_RAM_DATA_RAND, 32'hf00ff00f);
$display("--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers."); $display(
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x", dut.ram_addr_rand, dut.ram_data_rand); "--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: completed."); $display("--- test6: completed.");
$display(""); $display("");
end end
endtask // test6 endtask // test6
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -601,7 +600,7 @@ module tb_tk1();
$display("--- test7: completed."); $display("--- test7: completed.");
$display(""); $display("");
end end
endtask // test7 endtask // test7
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -629,7 +628,7 @@ module tb_tk1();
$display("--- test8: completed."); $display("--- test8: completed.");
$display(""); $display("");
end end
endtask // test8 endtask // test8
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -649,29 +648,29 @@ module tb_tk1();
write_word(ADDR_CPU_MON_CTRL, 32'h1); write_word(ADDR_CPU_MON_CTRL, 32'h1);
$display("--- test9: cpu_mon_first_reg: 0x%08x, cpu_mon_last_reg: 0x%08x", $display("--- test9: cpu_mon_first_reg: 0x%08x, cpu_mon_last_reg: 0x%08x",
dut.cpu_mon_first_reg, dut.cpu_mon_last_reg); dut.cpu_mon_first_reg, dut.cpu_mon_last_reg);
$display("--- test9: Try to redefine memory area after enabling monitor."); $display("--- test9: Try to redefine memory area after enabling monitor.");
write_word(ADDR_CPU_MON_FIRST, 32'hdeadbabe); write_word(ADDR_CPU_MON_FIRST, 32'hdeadbabe);
write_word(ADDR_CPU_MON_LAST, 32'hdeadcafe); write_word(ADDR_CPU_MON_LAST, 32'hdeadcafe);
$display("--- test9: cpu_mon_first_reg: 0x%08x, cpu_mon_last_reg: 0x%08x", $display("--- test9: cpu_mon_first_reg: 0x%08x, cpu_mon_last_reg: 0x%08x",
dut.cpu_mon_first_reg, dut.cpu_mon_last_reg); dut.cpu_mon_first_reg, dut.cpu_mon_last_reg);
$display("--- test9: force_trap before illegal access: 0x%1x", tb_force_trap); $display("--- test9: force_trap before illegal access: 0x%1x", tb_force_trap);
$display("--- test9: Creating an illegal access."); $display("--- test9: Creating an illegal access.");
tb_cpu_addr = 32'h13371337; tb_cpu_addr = 32'h13371337;
tb_cpu_instr = 1'h1; tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1; tb_cpu_valid = 1'h1;
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
$display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x", $display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x", tb_cpu_addr,
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid); tb_cpu_instr, tb_cpu_valid);
$display("--- test9: force_trap: 0x%1x", tb_force_trap); $display("--- test9: force_trap: 0x%1x", tb_force_trap);
$display("--- test9: completed."); $display("--- test9: completed.");
$display(""); $display("");
end end
endtask // test9 endtask // test9
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -680,7 +679,7 @@ module tb_tk1();
//---------------------------------------------------------------- //----------------------------------------------------------------
task test10; task test10;
begin begin
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
tb_monitor = 0; tb_monitor = 0;
tb_spi_monitor = 0; tb_spi_monitor = 0;
@ -698,7 +697,7 @@ module tb_tk1();
// Ready ready flag in SPI until it is set. // Ready ready flag in SPI until it is set.
read_word(ADDR_SPI_XFER); read_word(ADDR_SPI_XFER);
while (!tb_read_data) begin while (!tb_read_data) begin
read_word(ADDR_SPI_XFER); read_word(ADDR_SPI_XFER);
end end
$display("--- test10: Byte should have been sent."); $display("--- test10: Byte should have been sent.");
@ -713,42 +712,41 @@ module tb_tk1();
$display("--- test10: completed."); $display("--- test10: completed.");
$display(""); $display("");
end end
endtask // test10 endtask // test10
//---------------------------------------------------------------- //----------------------------------------------------------------
// tk1_test // tk1_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : tk1_test
begin : tk1_test $display("");
$display(""); $display(" -= Testbench for tk1 started =-");
$display(" -= Testbench for tk1 started =-"); $display(" ===========================");
$display(" ==========================="); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); test1();
test2(); test2();
test3(); test3();
test4(); test4();
test5(); test5();
test6(); test6();
test7(); test7();
test8(); test8();
test9(); test9();
test9(); test9();
test10(); test10();
display_test_result(); display_test_result();
$display(""); $display("");
$display(" -= Testbench for tk1 completed =-"); $display(" -= Testbench for tk1 completed =-");
$display(" ============================="); $display(" =============================");
$display(""); $display("");
$finish; $finish;
end // tk1_test end // tk1_test
endmodule // tb_tk1 endmodule // tb_tk1
//====================================================================== //======================================================================
// EOF tb_tk1.v // EOF tb_tk1.v

328
hw/application_fpga/core/tk1/tb/tb_tk1_spi_master.v
View File

@ -11,10 +11,9 @@
// //
//====================================================================== //======================================================================
`default_nettype none `default_nettype none `timescale 1ns / 1ns
`timescale 1ns / 1ns
module tb_tk1_spi_master(); module tb_tk1_spi_master ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
@ -22,22 +21,22 @@ module tb_tk1_spi_master();
parameter DEBUG = 1; parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter MISO_ALL_ZERO = 0; parameter MISO_ALL_ZERO = 0;
parameter MISO_ALL_ONE = 1; parameter MISO_ALL_ONE = 1;
parameter MISO_MOSI = 2; parameter MISO_MOSI = 2;
parameter MISO_INV_MOSI = 3; parameter MISO_INV_MOSI = 3;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg monitor; reg monitor;
reg verbose; reg verbose;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
@ -48,17 +47,17 @@ module tb_tk1_spi_master();
reg tb_spi_enable; reg tb_spi_enable;
reg tb_spi_enable_vld; reg tb_spi_enable_vld;
reg tb_spi_start; reg tb_spi_start;
reg [7 : 0] tb_spi_tx_data; reg [ 7 : 0] tb_spi_tx_data;
reg tb_spi_tx_data_vld; reg tb_spi_tx_data_vld;
wire [7 : 0] tb_spi_rx_data; wire [ 7 : 0] tb_spi_rx_data;
wire tb_spi_ready; wire tb_spi_ready;
wire mem_model_WPn; wire mem_model_WPn;
wire mem_model_HOLDn; wire mem_model_HOLDn;
reg [1 : 0] tb_miso_mux_ctrl; reg [ 1 : 0] tb_miso_mux_ctrl;
reg my_tb_spi_ss; reg my_tb_spi_ss;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -70,36 +69,36 @@ module tb_tk1_spi_master();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
tk1_spi_master dut( tk1_spi_master dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.spi_ss(tb_spi_ss), .spi_ss (tb_spi_ss),
.spi_sck(tb_spi_sck), .spi_sck (tb_spi_sck),
.spi_mosi(tb_spi_mosi), .spi_mosi(tb_spi_mosi),
.spi_miso(tb_spi_miso), .spi_miso(tb_spi_miso),
.spi_enable(tb_spi_enable), .spi_enable(tb_spi_enable),
.spi_enable_vld(tb_spi_enable_vld), .spi_enable_vld(tb_spi_enable_vld),
.spi_start(tb_spi_start), .spi_start(tb_spi_start),
.spi_tx_data(tb_spi_tx_data), .spi_tx_data(tb_spi_tx_data),
.spi_tx_data_vld(tb_spi_tx_data_vld), .spi_tx_data_vld(tb_spi_tx_data_vld),
.spi_rx_data(tb_spi_rx_data), .spi_rx_data(tb_spi_rx_data),
.spi_ready(tb_spi_ready) .spi_ready(tb_spi_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// spi_memory // spi_memory
//---------------------------------------------------------------- //----------------------------------------------------------------
W25Q80DL spi_memory( W25Q80DL spi_memory (
.CSn(tb_spi_ss), .CSn(tb_spi_ss),
.CLK(tb_spi_sck), .CLK(tb_spi_sck),
.DIO(tb_spi_mosi), .DIO(tb_spi_mosi),
.DO(tb_spi_miso), .DO(tb_spi_miso),
.WPn(mem_model_WPn), .WPn(mem_model_WPn),
.HOLDn(mem_model_HOLDn) .HOLDn(mem_model_HOLDn)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -107,11 +106,10 @@ module tb_tk1_spi_master();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -120,15 +118,13 @@ module tb_tk1_spi_master();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (monitor) begin
if (monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -142,54 +138,52 @@ module tb_tk1_spi_master();
$display("State of DUT at cycle: %08d", cycle_ctr); $display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------"); $display("------------");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x", $display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x", dut.spi_ss,
dut.spi_ss, dut.spi_sck, dut.spi_mosi, dut.spi_miso); dut.spi_sck, dut.spi_mosi, dut.spi_miso);
$display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x", $display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x", dut.spi_enable_vld, dut.spi_enable);
dut.spi_enable_vld, dut.spi_enable); $display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x", dut.spi_tx_data_vld, dut.spi_tx_data);
$display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x", $display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x", dut.spi_start,
dut.spi_tx_data_vld, dut.spi_tx_data); dut.spi_ready, dut.spi_rx_data);
$display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x",
dut.spi_start, dut.spi_ready, dut.spi_rx_data);
$display(""); $display("");
$display(""); $display("");
$display("Internal state:"); $display("Internal state:");
$display("spi_bit_ctr_rst: 0x%1x, spi_bit_ctr_inc: 0x%1x, spi_bit_ctr_reg: 0x%02x", $display("spi_bit_ctr_rst: 0x%1x, spi_bit_ctr_inc: 0x%1x, spi_bit_ctr_reg: 0x%02x",
dut.spi_bit_ctr_rst, dut.spi_bit_ctr_inc, dut.spi_bit_ctr_reg); dut.spi_bit_ctr_rst, dut.spi_bit_ctr_inc, dut.spi_bit_ctr_reg);
$display(""); $display("");
$display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x", $display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x", dut.spi_ctrl_reg,
dut.spi_ctrl_reg, dut.spi_ctrl_new, dut.spi_ctrl_we); dut.spi_ctrl_new, dut.spi_ctrl_we);
$display(""); $display("");
$display("spi_tx_data_new: 0x%1x, spi_tx_data_nxt: 0x%1x, spi_tx_data_we: 0x%1x", $display("spi_tx_data_new: 0x%1x, spi_tx_data_nxt: 0x%1x, spi_tx_data_we: 0x%1x",
dut.spi_tx_data_new, dut.spi_tx_data_nxt, dut.spi_tx_data_we); dut.spi_tx_data_new, dut.spi_tx_data_nxt, dut.spi_tx_data_we);
$display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x", $display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x", dut.spi_tx_data_reg,
dut.spi_tx_data_reg, dut.spi_tx_data_new); dut.spi_tx_data_new);
$display(""); $display("");
$display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x", $display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x", dut.spi_rx_data_nxt,
dut.spi_rx_data_nxt, dut.spi_rx_data_we); dut.spi_rx_data_we);
$display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x", $display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x", dut.spi_rx_data_reg,
dut.spi_rx_data_reg, dut.spi_rx_data_new); dut.spi_rx_data_new);
$display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x", $display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x", dut.spi_rx_data_reg[0],
dut.spi_rx_data_reg[0], dut.spi_rx_data_new[0]); dut.spi_rx_data_new[0]);
$display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x", $display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x", dut.spi_rx_data_reg[1],
dut.spi_rx_data_reg[1], dut.spi_rx_data_new[1]); dut.spi_rx_data_new[1]);
$display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x", $display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x", dut.spi_rx_data_reg[2],
dut.spi_rx_data_reg[2], dut.spi_rx_data_new[2]); dut.spi_rx_data_new[2]);
$display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x", $display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x", dut.spi_rx_data_reg[3],
dut.spi_rx_data_reg[3], dut.spi_rx_data_new[3]); dut.spi_rx_data_new[3]);
$display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x", $display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x", dut.spi_rx_data_reg[4],
dut.spi_rx_data_reg[4], dut.spi_rx_data_new[4]); dut.spi_rx_data_new[4]);
$display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x", $display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x", dut.spi_rx_data_reg[5],
dut.spi_rx_data_reg[5], dut.spi_rx_data_new[5]); dut.spi_rx_data_new[5]);
$display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x", $display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x", dut.spi_rx_data_reg[6],
dut.spi_rx_data_reg[6], dut.spi_rx_data_new[6]); dut.spi_rx_data_new[6]);
$display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x", $display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x", dut.spi_rx_data_reg[7],
dut.spi_rx_data_reg[7], dut.spi_rx_data_new[7]); dut.spi_rx_data_new[7]);
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -204,7 +198,7 @@ module tb_tk1_spi_master();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -214,17 +208,15 @@ module tb_tk1_spi_master();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("--- All %02d test cases completed successfully", tc_ctr);
$display("--- All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("--- %02d tests completed - %02d test cases did not complete successfully.",
begin tc_ctr, error_ctr);
$display("--- %02d tests completed - %02d test cases did not complete successfully.", end
tc_ctr, error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -235,10 +227,10 @@ module tb_tk1_spi_master();
//---------------------------------------------------------------- //----------------------------------------------------------------
task init_sim; task init_sim;
begin begin
cycle_ctr = 0; cycle_ctr = 0;
error_ctr = 0; error_ctr = 0;
tc_ctr = 0; tc_ctr = 0;
monitor = 0; monitor = 0;
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
@ -249,7 +241,7 @@ module tb_tk1_spi_master();
tb_spi_tx_data_vld = 1'h0; tb_spi_tx_data_vld = 1'h0;
tb_miso_mux_ctrl = MISO_MOSI; tb_miso_mux_ctrl = MISO_MOSI;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -260,7 +252,7 @@ module tb_tk1_spi_master();
task enable_spi; task enable_spi;
begin begin
if (verbose) begin if (verbose) begin
$display("enable_spi: Started"); $display("enable_spi: Started");
end end
tb_spi_enable = 1'h1; tb_spi_enable = 1'h1;
@ -270,10 +262,10 @@ module tb_tk1_spi_master();
#(CLK_PERIOD); #(CLK_PERIOD);
if (verbose) begin if (verbose) begin
$display("enable_spi: Completed"); $display("enable_spi: Completed");
end end
end end
endtask // enable_spi endtask // enable_spi
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -284,7 +276,7 @@ module tb_tk1_spi_master();
task disable_spi; task disable_spi;
begin begin
if (verbose) begin if (verbose) begin
$display("disable_spi: Started"); $display("disable_spi: Started");
end end
tb_spi_enable = 1'h0; tb_spi_enable = 1'h0;
@ -294,10 +286,10 @@ module tb_tk1_spi_master();
#(CLK_PERIOD); #(CLK_PERIOD);
if (verbose) begin if (verbose) begin
$display("disable_spi: Completed"); $display("disable_spi: Completed");
end end
end end
endtask // disable_spi endtask // disable_spi
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -306,10 +298,10 @@ module tb_tk1_spi_master();
// Wait until the SPI-master is ready, then send input byte // Wait until the SPI-master is ready, then send input byte
// and return the received byte. // and return the received byte.
//---------------------------------------------------------------- //----------------------------------------------------------------
task xfer_byte (input [7 : 0] to_mem, output [7 : 0] from_mem); task xfer_byte(input [7 : 0] to_mem, output [7 : 0] from_mem);
begin begin
if (verbose) begin if (verbose) begin
$display("xfer_byte: Trying to send 0x%02x to mem", to_mem); $display("xfer_byte: Trying to send 0x%02x to mem", to_mem);
end end
tb_spi_tx_data = to_mem; tb_spi_tx_data = to_mem;
@ -319,7 +311,7 @@ module tb_tk1_spi_master();
#(CLK_PERIOD); #(CLK_PERIOD);
while (tb_spi_ready == 1'h0) begin while (tb_spi_ready == 1'h0) begin
#(CLK_PERIOD); #(CLK_PERIOD);
end end
#(CLK_PERIOD); #(CLK_PERIOD);
@ -329,17 +321,17 @@ module tb_tk1_spi_master();
#(CLK_PERIOD); #(CLK_PERIOD);
while (tb_spi_ready == 1'h0) begin while (tb_spi_ready == 1'h0) begin
#(CLK_PERIOD); #(CLK_PERIOD);
end end
#(CLK_PERIOD); #(CLK_PERIOD);
from_mem = tb_spi_rx_data; from_mem = tb_spi_rx_data;
#(CLK_PERIOD); #(CLK_PERIOD);
if (verbose) begin if (verbose) begin
$display("xfer_byte: Received 0x%02x from mem", from_mem); $display("xfer_byte: Received 0x%02x from mem", from_mem);
end end
end end
endtask // xfer_byte endtask // xfer_byte
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -347,13 +339,14 @@ module tb_tk1_spi_master();
// //
// Read out a specified memory range. Result is printed, // Read out a specified memory range. Result is printed,
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_mem_range (input [23 : 0] address, input integer num_bytes); task read_mem_range(input [23 : 0] address, input integer num_bytes);
begin : read_mem_range begin : read_mem_range
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
integer i; integer i;
if (verbose) begin if (verbose) begin
$display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes, address); $display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes,
address);
end end
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
@ -369,27 +362,27 @@ module tb_tk1_spi_master();
xfer_byte(address[7 : 0], rx_byte); xfer_byte(address[7 : 0], rx_byte);
// Read out num_bytes bytes. // Read out num_bytes bytes.
for (i = 0 ; i < num_bytes ; i = i + 1) begin for (i = 0; i < num_bytes; i = i + 1) begin
xfer_byte(8'h00, rx_byte); xfer_byte(8'h00, rx_byte);
$display("--- tc_read_mem_range: Byte 0x%06x: 0x%02x", address + i, rx_byte); $display("--- tc_read_mem_range: Byte 0x%06x: 0x%02x", address + i, rx_byte);
end end
disable_spi(); disable_spi();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
if (verbose) begin if (verbose) begin
$display("read_mem_range: Completed"); $display("read_mem_range: Completed");
end end
end end
endtask // read_mem_range endtask // read_mem_range
//---------------------------------------------------------------- //----------------------------------------------------------------
// read_status() // read_status()
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_status (); task read_status();
begin : read_status begin : read_status
reg [7 : 0] dummy; reg [ 7 : 0] dummy;
reg [15 : 0] status; reg [15 : 0] status;
enable_spi(); enable_spi();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
@ -400,7 +393,7 @@ module tb_tk1_spi_master();
disable_spi(); disable_spi();
$display("--- read_status: 0x%04x", status); $display("--- read_status: 0x%04x", status);
end end
endtask // read_status endtask // read_status
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -411,7 +404,7 @@ module tb_tk1_spi_master();
task tc_get_device_id; task tc_get_device_id;
begin : tc_get_id begin : tc_get_id
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
monitor = 0; monitor = 0;
$display(""); $display("");
@ -452,7 +445,7 @@ module tb_tk1_spi_master();
$display("--- tc_get_device_id: completed."); $display("--- tc_get_device_id: completed.");
$display(""); $display("");
end end
endtask // tc_get_device_id endtask // tc_get_device_id
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -463,7 +456,7 @@ module tb_tk1_spi_master();
task tc_get_jedec_id; task tc_get_jedec_id;
begin : tc_get_id begin : tc_get_id
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
monitor = 0; monitor = 0;
verbose = 0; verbose = 0;
@ -494,7 +487,7 @@ module tb_tk1_spi_master();
verbose = 1; verbose = 1;
end end
endtask // tc_get_jedec_id endtask // tc_get_jedec_id
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -507,7 +500,7 @@ module tb_tk1_spi_master();
begin : tc_get_id begin : tc_get_id
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
integer i; integer i;
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
monitor = 0; monitor = 0;
verbose = 0; verbose = 0;
@ -531,9 +524,9 @@ module tb_tk1_spi_master();
// Send eight bytes and get unique device id back. // Send eight bytes and get unique device id back.
$display("--- tc_get_unique_device_id: reading out the unique device ID"); $display("--- tc_get_unique_device_id: reading out the unique device ID");
for (i = 0 ; i < 8 ; i = i + 1) begin for (i = 0; i < 8; i = i + 1) begin
xfer_byte(8'h00, rx_byte); xfer_byte(8'h00, rx_byte);
$display("--- tc_get_unique_device_id: 0x%02x", rx_byte); $display("--- tc_get_unique_device_id: 0x%02x", rx_byte);
end end
disable_spi(); disable_spi();
@ -544,7 +537,7 @@ module tb_tk1_spi_master();
verbose = 1; verbose = 1;
end end
endtask // tc_get_unique_device_id endtask // tc_get_unique_device_id
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -555,7 +548,7 @@ module tb_tk1_spi_master();
task tc_get_manufacturer_id; task tc_get_manufacturer_id;
begin : tc_get_id begin : tc_get_id
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
monitor = 0; monitor = 0;
$display(""); $display("");
@ -589,7 +582,7 @@ module tb_tk1_spi_master();
$display("--- tc_get_manufacturer_id: completed."); $display("--- tc_get_manufacturer_id: completed.");
$display(""); $display("");
end end
endtask // tc_get_manufacturer_id endtask // tc_get_manufacturer_id
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -601,7 +594,7 @@ module tb_tk1_spi_master();
begin : tc_get_id begin : tc_get_id
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
integer i; integer i;
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
monitor = 0; monitor = 0;
verbose = 0; verbose = 0;
@ -624,9 +617,9 @@ module tb_tk1_spi_master();
// Read out 16 bytes. // Read out 16 bytes.
$display("--- tc_read_mem: Reading out 16 bytes from the memory."); $display("--- tc_read_mem: Reading out 16 bytes from the memory.");
for (i = 1 ; i < 17 ; i = i + 1) begin for (i = 1; i < 17; i = i + 1) begin
xfer_byte(8'h00, rx_byte); xfer_byte(8'h00, rx_byte);
$display("--- tc_read_mem: Byte %d: 0x%02x", i, rx_byte); $display("--- tc_read_mem: Byte %d: 0x%02x", i, rx_byte);
end end
disable_spi(); disable_spi();
@ -635,7 +628,7 @@ module tb_tk1_spi_master();
$display("--- tc_read_mem: completed."); $display("--- tc_read_mem: completed.");
$display(""); $display("");
end end
endtask // tc_read_mem endtask // tc_read_mem
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -649,7 +642,7 @@ module tb_tk1_spi_master();
begin : tc_get_id begin : tc_get_id
reg [7 : 0] rx_byte; reg [7 : 0] rx_byte;
integer i; integer i;
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
monitor = 0; monitor = 0;
verbose = 0; verbose = 0;
@ -663,9 +656,9 @@ module tb_tk1_spi_master();
// Set write enable mode. // Set write enable mode.
enable_spi(); enable_spi();
// #(2 * CLK_PERIOD); // #(2 * CLK_PERIOD);
xfer_byte(8'h06, rx_byte); xfer_byte(8'h06, rx_byte);
// #(2 * CLK_PERIOD); // #(2 * CLK_PERIOD);
disable_spi(); disable_spi();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
$display("--- tc_rmr_mem: Status after write enable:"); $display("--- tc_rmr_mem: Status after write enable:");
@ -689,40 +682,39 @@ module tb_tk1_spi_master();
$display("--- tc_rmr_mem: completed."); $display("--- tc_rmr_mem: completed.");
$display(""); $display("");
end end
endtask // tc_rmr_mem endtask // tc_rmr_mem
//---------------------------------------------------------------- //----------------------------------------------------------------
// tk1_spi_master_test // tk1_spi_master_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : tk1_spi_master_test
begin : tk1_spi_master_test $display("");
$display(""); $display(" -= Testbench for tk1_spi_master started =-");
$display(" -= Testbench for tk1_spi_master started =-"); $display(" =======================================");
$display(" ======================================="); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
disable_spi(); disable_spi();
verbose = 1; verbose = 1;
// tc_get_device_id(); // tc_get_device_id();
tc_get_jedec_id(); tc_get_jedec_id();
// tc_get_manufacturer_id(); // tc_get_manufacturer_id();
tc_get_unique_device_id(); tc_get_unique_device_id();
tc_read_mem(); tc_read_mem();
// tc_rmr_mem(); // tc_rmr_mem();
display_test_result(); display_test_result();
$display(""); $display("");
$display(" -= Testbench for tk1_spi_master completed =-"); $display(" -= Testbench for tk1_spi_master completed =-");
$display(" ========================================="); $display(" =========================================");
$display(""); $display("");
$finish; $finish;
end // tk1_spi_master_test end // tk1_spi_master_test
endmodule // tb_tk1_spi_master endmodule // tb_tk1_spi_master
//====================================================================== //======================================================================
// EOF tb_tk1_spi_master.v // EOF tb_tk1_spi_master.v

23
hw/application_fpga/core/tk1/tb/udi_rom_sim.v
View File

@ -12,24 +12,23 @@
//====================================================================== //======================================================================
module udi_rom ( module udi_rom (
input wire [0:0] addr, input wire [ 0:0] addr,
output wire [31:0] data output wire [31:0] data
); );
reg [31 : 0] tmp_data; reg [31 : 0] tmp_data;
assign data = tmp_data; assign data = tmp_data;
always @* always @* begin : addr_mux
begin : addr_mux if (addr) begin
if (addr) begin tmp_data = 32'h04050607;
tmp_data = 32'h04050607;
end
else begin
tmp_data = 32'h00010203;
end
end end
else begin
tmp_data = 32'h00010203;
end
end
endmodule // udi_rom endmodule // udi_rom
//====================================================================== //======================================================================
// EOF udi_rom_sim.v // EOF udi_rom_sim.v

208
hw/application_fpga/core/touch_sense/rtl/touch_sense.v
View File

@ -13,47 +13,47 @@
`default_nettype none `default_nettype none
module touch_sense( module touch_sense (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire touch_event, input wire touch_event,
input wire cs, input wire cs,
input wire we, input wire we,
input wire [7 : 0] address, input wire [ 7 : 0] address,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_EVENT_BIT = 0; localparam STATUS_EVENT_BIT = 0;
localparam CTRL_IDLE = 2'h0; localparam CTRL_IDLE = 2'h0;
localparam CTRL_EVENT = 2'h1; localparam CTRL_EVENT = 2'h1;
localparam CTRL_WAIT = 2'h2; localparam CTRL_WAIT = 2'h2;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg touch_event_sample0_reg; reg touch_event_sample0_reg;
reg touch_event_sample1_reg; reg touch_event_sample1_reg;
reg touch_event_reg; reg touch_event_reg;
reg touch_event_new; reg touch_event_new;
reg touch_event_set; reg touch_event_set;
reg touch_event_rst; reg touch_event_rst;
reg touch_event_we; reg touch_event_we;
reg [1 : 0] touch_sense_ctrl_reg; reg [ 1 : 0] touch_sense_ctrl_reg;
reg [1 : 0] touch_sense_ctrl_new; reg [ 1 : 0] touch_sense_ctrl_new;
reg touch_sense_ctrl_we; reg touch_sense_ctrl_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -74,117 +74,113 @@ module touch_sense(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin touch_sense_ctrl_reg <= CTRL_IDLE;
touch_sense_ctrl_reg <= CTRL_IDLE; touch_event_sample0_reg <= 1'h0;
touch_event_sample0_reg <= 1'h0; touch_event_sample1_reg <= 1'h0;
touch_event_sample1_reg <= 1'h0; touch_event_reg <= 1'h0;
touch_event_reg <= 1'h0; end
else begin
touch_event_sample0_reg <= touch_event;
touch_event_sample1_reg <= touch_event_sample0_reg;
if (touch_event_we) begin
touch_event_reg <= touch_event_new;
end end
else begin if (touch_sense_ctrl_we) begin
touch_event_sample0_reg <= touch_event; touch_sense_ctrl_reg <= touch_sense_ctrl_new;
touch_event_sample1_reg <= touch_event_sample0_reg;
if (touch_event_we) begin
touch_event_reg <= touch_event_new;
end
if (touch_sense_ctrl_we) begin
touch_sense_ctrl_reg <= touch_sense_ctrl_new;
end
end end
end // reg_update end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
// api // api
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api api_clear_event = 1'h0;
api_clear_event = 1'h0; tmp_read_data = 32'h0;
tmp_read_data = 32'h0; tmp_ready = 1'h0;
tmp_ready = 1'h0;
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (we) begin if (we) begin
if (address == ADDR_STATUS) begin if (address == ADDR_STATUS) begin
api_clear_event = 1'h1; api_clear_event = 1'h1;
end
end
else begin
if (address == ADDR_STATUS) begin
tmp_read_data[STATUS_EVENT_BIT] = touch_event_reg;
end
end end
end end
end // api
else begin
if (address == ADDR_STATUS) begin
tmp_read_data[STATUS_EVENT_BIT] = touch_event_reg;
end
end
end
end // api
//---------------------------------------------------------------- //----------------------------------------------------------------
// touch_event_reg_logic // touch_event_reg_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : touch_event_reg_logic
begin : touch_event_reg_logic touch_event_new = 1'h0;
touch_event_new = 1'h0; touch_event_we = 1'h0;
touch_event_we = 1'h0;
if (touch_event_set) begin if (touch_event_set) begin
touch_event_new = 1'h1; touch_event_new = 1'h1;
touch_event_we = 1'h1; touch_event_we = 1'h1;
end
else if (touch_event_rst) begin
touch_event_new = 1'h0;
touch_event_we = 1'h1;
end
end end
else if (touch_event_rst) begin
touch_event_new = 1'h0;
touch_event_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// touch_sense_ctrl // touch_sense_ctrl
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : touch_sense_ctrl
begin : touch_sense_ctrl touch_event_set = 1'h0;
touch_event_set = 1'h0; touch_event_rst = 1'h0;
touch_event_rst = 1'h0; touch_sense_ctrl_new = CTRL_IDLE;
touch_sense_ctrl_new = CTRL_IDLE; touch_sense_ctrl_we = 1'h0;
touch_sense_ctrl_we = 1'h0;
case (touch_sense_ctrl_reg) case (touch_sense_ctrl_reg)
CTRL_IDLE : begin CTRL_IDLE: begin
if (touch_event_sample1_reg) begin if (touch_event_sample1_reg) begin
touch_event_set = 1'h1; touch_event_set = 1'h1;
touch_sense_ctrl_new = CTRL_EVENT; touch_sense_ctrl_new = CTRL_EVENT;
touch_sense_ctrl_we = 1'h1; touch_sense_ctrl_we = 1'h1;
end end
end end
CTRL_EVENT: begin CTRL_EVENT: begin
if (api_clear_event) begin if (api_clear_event) begin
touch_event_rst = 1'h1; touch_event_rst = 1'h1;
touch_sense_ctrl_new = CTRL_WAIT; touch_sense_ctrl_new = CTRL_WAIT;
touch_sense_ctrl_we = 1'h1; touch_sense_ctrl_we = 1'h1;
end end
end end
CTRL_WAIT: begin CTRL_WAIT: begin
if (!touch_event_sample1_reg) begin if (!touch_event_sample1_reg) begin
touch_sense_ctrl_new = CTRL_IDLE; touch_sense_ctrl_new = CTRL_IDLE;
touch_sense_ctrl_we = 1'h1; touch_sense_ctrl_we = 1'h1;
end end
end end
default : begin default: begin
end end
endcase // case (touch_sense_ctrl_reg) endcase // case (touch_sense_ctrl_reg)
end end
endmodule // touch_sense endmodule // touch_sense
//====================================================================== //======================================================================
// EOF touch_sense.v // EOF touch_sense.v

160
hw/application_fpga/core/touch_sense/tb/tb_touch_sense.v
View File

@ -13,54 +13,54 @@
`default_nettype none `default_nettype none
module tb_touch_sense(); module tb_touch_sense ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 1; parameter DEBUG = 1;
parameter DUMP_WAIT = 0; parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0; localparam STATUS_READY_BIT = 0;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_monitor; reg tb_monitor;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_touch_event; reg tb_touch_event;
reg tb_cs; reg tb_cs;
reg tb_we; reg tb_we;
reg [7 : 0] tb_address; reg [ 7 : 0] tb_address;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
reg [31 : 0] read_data; reg [31 : 0] read_data;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
touch_sense dut( touch_sense dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.touch_event(tb_touch_event), .touch_event(tb_touch_event),
.cs(tb_cs), .cs(tb_cs),
.we(tb_we), .we(tb_we),
.address(tb_address), .address(tb_address),
.read_data(tb_read_data) .read_data(tb_read_data)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -68,11 +68,10 @@ module tb_touch_sense();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -81,15 +80,13 @@ module tb_touch_sense();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (tb_monitor) begin
if (tb_monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -104,7 +101,7 @@ module tb_touch_sense();
$display("Cycle: %08d", cycle_ctr); $display("Cycle: %08d", cycle_ctr);
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -119,7 +116,7 @@ module tb_touch_sense();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -129,17 +126,15 @@ module tb_touch_sense();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("--- All %02d test cases completed successfully", tc_ctr);
$display("--- All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("--- %02d tests completed - %02d test cases did not complete successfully.",
begin tc_ctr, error_ctr);
$display("--- %02d tests completed - %02d test cases did not complete successfully.", end
tc_ctr, error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -150,10 +145,10 @@ module tb_touch_sense();
//---------------------------------------------------------------- //----------------------------------------------------------------
task init_sim; task init_sim;
begin begin
cycle_ctr = 0; cycle_ctr = 0;
error_ctr = 0; error_ctr = 0;
tc_ctr = 0; tc_ctr = 0;
tb_monitor = 0; tb_monitor = 0;
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
@ -162,7 +157,7 @@ module tb_touch_sense();
tb_we = 1'h0; tb_we = 1'h0;
tb_address = 8'h0; tb_address = 8'h0;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -170,14 +165,12 @@ module tb_touch_sense();
// //
// Write the given word to the DUT using the DUT interface. // Write the given word to the DUT using the DUT interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
task write_word(input [7 : 0] address, task write_word(input [7 : 0] address, input [31 : 0] word);
input [31 : 0] word);
begin begin
if (DEBUG) if (DEBUG) begin
begin $display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("");
$display(""); end
end
tb_address = address; tb_address = address;
tb_cs = 1; tb_cs = 1;
@ -186,7 +179,7 @@ module tb_touch_sense();
tb_cs = 0; tb_cs = 0;
tb_we = 0; tb_we = 0;
end end
endtask // write_word endtask // write_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -196,7 +189,7 @@ module tb_touch_sense();
// the word read will be available in the global variable // the word read will be available in the global variable
// read_data. // read_data.
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_word(input [7 : 0] address); task read_word(input [7 : 0] address);
begin begin
tb_address = address; tb_address = address;
tb_cs = 1; tb_cs = 1;
@ -205,13 +198,12 @@ module tb_touch_sense();
read_data = tb_read_data; read_data = tb_read_data;
tb_cs = 0; tb_cs = 0;
if (DEBUG) if (DEBUG) begin
begin $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("");
$display(""); end
end
end end
endtask // read_word endtask // read_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -222,10 +214,9 @@ module tb_touch_sense();
task wait_ready; task wait_ready;
begin : wready begin : wready
read_word(ADDR_STATUS); read_word(ADDR_STATUS);
while (read_data == 0) while (read_data == 0) read_word(ADDR_STATUS);
read_word(ADDR_STATUS);
end end
endtask // wait_ready endtask // wait_ready
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -279,32 +270,31 @@ module tb_touch_sense();
$display("--- test1: completed."); $display("--- test1: completed.");
$display(""); $display("");
end end
endtask // test1 endtask // test1
//---------------------------------------------------------------- //----------------------------------------------------------------
// touch_sense_test // touch_sense_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : timer_test
begin : timer_test $display("");
$display(""); $display(" -= Testbench for touch_sense started =-");
$display(" -= Testbench for touch_sense started =-"); $display(" ====================================");
$display(" ===================================="); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); test1();
display_test_result(); display_test_result();
$display(""); $display("");
$display(" -= Testbench for touch_sense completed =-"); $display(" -= Testbench for touch_sense completed =-");
$display(" ======================================"); $display(" ======================================");
$display(""); $display("");
$finish; $finish;
end // touch_sense_test end // touch_sense_test
endmodule // tb_touch_sense endmodule // tb_touch_sense
//====================================================================== //======================================================================
// EOF tb_touch_sense.v // EOF tb_touch_sense.v

369
hw/application_fpga/core/trng/rtl/rosc.v
View File

@ -16,77 +16,77 @@
`default_nettype none `default_nettype none
module rosc( module rosc (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire cs, input wire cs,
input wire we, input wire we,
input wire [7 : 0] address, input wire [ 7 : 0] address,
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
input wire [31 : 0] write_data, input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */ /* verilator lint_on UNUSED */
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
// API // API
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam ADDR_ENTROPY = 8'h20; localparam ADDR_ENTROPY = 8'h20;
// Total number of ROSCs will be 2 x NUM_ROSC. // Total number of ROSCs will be 2 x NUM_ROSC.
localparam SAMPLE_CYCLES = 16'h1000; localparam SAMPLE_CYCLES = 16'h1000;
localparam NUM_ROSC = 16; localparam NUM_ROSC = 16;
localparam SKIP_BITS = 32; localparam SKIP_BITS = 32;
localparam CTRL_SAMPLE1 = 0; localparam CTRL_SAMPLE1 = 0;
localparam CTRL_SAMPLE2 = 1; localparam CTRL_SAMPLE2 = 1;
localparam CTRL_DATA_READY = 2; localparam CTRL_DATA_READY = 2;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers with associated wires. // Registers with associated wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [15 : 0] cycle_ctr_reg; reg [ 15 : 0] cycle_ctr_reg;
reg [15 : 0] cycle_ctr_new; reg [ 15 : 0] cycle_ctr_new;
reg cycle_ctr_done; reg cycle_ctr_done;
reg cycle_ctr_rst; reg cycle_ctr_rst;
reg [7 : 0] bit_ctr_reg; reg [ 7 : 0] bit_ctr_reg;
reg [7 : 0] bit_ctr_new; reg [ 7 : 0] bit_ctr_new;
reg bit_ctr_inc; reg bit_ctr_inc;
reg bit_ctr_rst; reg bit_ctr_rst;
reg bit_ctr_we; reg bit_ctr_we;
reg [31 : 0] entropy_reg; reg [ 31 : 0] entropy_reg;
reg [31 : 0] entropy_new; reg [ 31 : 0] entropy_new;
reg entropy_we; reg entropy_we;
reg [1 : 0] sample1_reg; reg [ 1 : 0] sample1_reg;
reg [1 : 0] sample1_new; reg [ 1 : 0] sample1_new;
reg sample1_we; reg sample1_we;
reg [1 : 0] sample2_reg; reg [ 1 : 0] sample2_reg;
reg [1 : 0] sample2_new; reg [ 1 : 0] sample2_new;
reg sample2_we; reg sample2_we;
reg data_ready_reg; reg data_ready_reg;
reg data_ready_new; reg data_ready_new;
reg data_ready_we; reg data_ready_we;
reg [1 : 0] rosc_ctrl_reg; reg [ 1 : 0] rosc_ctrl_reg;
reg [1 : 0] rosc_ctrl_new; reg [ 1 : 0] rosc_ctrl_new;
reg rosc_ctrl_we; reg rosc_ctrl_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] tmp_read_data; reg [ 31 : 0] tmp_read_data;
reg tmp_ready; reg tmp_ready;
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
wire [(NUM_ROSC - 1) : 0] f; wire [(NUM_ROSC - 1) : 0] f;
@ -111,62 +111,71 @@ module rosc(
//---------------------------------------------------------------- //----------------------------------------------------------------
genvar i; genvar i;
generate generate
for(i = 0 ; i < NUM_ROSC ; i = i + 1) for (i = 0; i < NUM_ROSC; i = i + 1) begin : oscillators
begin: oscillators /* verilator lint_off PINMISSING */
/* verilator lint_off PINMISSING */ /* verilator lint_off UNOPTFLAT */
/* verilator lint_off UNOPTFLAT */ (* keep *)
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_f (.I0(f[i]), .O(f[i])); SB_LUT4 #(
.LUT_INIT(16'h1)
) osc_inv_f (
.I0(f[i]),
.O (f[i])
);
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_g (.I0(g[i]), .O(g[i])); (* keep *) SB_LUT4 #(
/* verilator lint_on UNOPTFLAT */ .LUT_INIT(16'h1)
/* verilator lint_on PINMISSING */ ) osc_inv_g (
end .I0(g[i]),
.O (g[i])
);
/* verilator lint_on UNOPTFLAT */
/* verilator lint_on PINMISSING */
end
endgenerate endgenerate
//--------------------------------------------------------------- //---------------------------------------------------------------
// reg_update // reg_update
//--------------------------------------------------------------- //---------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin cycle_ctr_reg <= 16'h0;
cycle_ctr_reg <= 16'h0; bit_ctr_reg <= 8'h0;
bit_ctr_reg <= 8'h0; sample1_reg <= 2'h0;
sample1_reg <= 2'h0; sample2_reg <= 2'h0;
sample2_reg <= 2'h0; entropy_reg <= 32'h0;
entropy_reg <= 32'h0; data_ready_reg <= 1'h0;
data_ready_reg <= 1'h0; rosc_ctrl_reg <= CTRL_SAMPLE1;
rosc_ctrl_reg <= CTRL_SAMPLE1; end
end
else begin else begin
cycle_ctr_reg <= cycle_ctr_new; cycle_ctr_reg <= cycle_ctr_new;
if (bit_ctr_we) begin if (bit_ctr_we) begin
bit_ctr_reg <= bit_ctr_new; bit_ctr_reg <= bit_ctr_new;
end end
if (sample1_we) begin if (sample1_we) begin
sample1_reg <= sample1_new; sample1_reg <= sample1_new;
end end
if (sample2_we) begin if (sample2_we) begin
sample2_reg <= sample2_new; sample2_reg <= sample2_new;
end end
if (entropy_we) begin if (entropy_we) begin
entropy_reg <= entropy_new; entropy_reg <= entropy_new;
end end
if (data_ready_we) begin if (data_ready_we) begin
data_ready_reg <= data_ready_new; data_ready_reg <= data_ready_new;
end end
if (rosc_ctrl_we) begin if (rosc_ctrl_we) begin
rosc_ctrl_reg <= rosc_ctrl_new; rosc_ctrl_reg <= rosc_ctrl_new;
end end
end end
end end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -174,136 +183,132 @@ module rosc(
// //
// The interface command decoding logic. // The interface command decoding logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api bit_ctr_rst = 1'h0;
bit_ctr_rst = 1'h0; tmp_read_data = 32'h0;
tmp_read_data = 32'h0; tmp_ready = 1'h0;
tmp_ready = 1'h0;
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (!we) begin if (!we) begin
if (address == ADDR_STATUS) begin if (address == ADDR_STATUS) begin
tmp_read_data = {31'h0, data_ready_reg}; tmp_read_data = {31'h0, data_ready_reg};
end end
if (address == ADDR_ENTROPY) begin if (address == ADDR_ENTROPY) begin
tmp_read_data = entropy_reg; tmp_read_data = entropy_reg;
bit_ctr_rst = 1'h1; bit_ctr_rst = 1'h1;
end end
end
end end
end // api end
end // api
//---------------------------------------------------------------- //----------------------------------------------------------------
// bit_ctr_logic // bit_ctr_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : bit_ctr_logic
begin : bit_ctr_logic bit_ctr_new = 8'h0;
bit_ctr_we = 1'h0;
data_ready_new = 1'h0;
data_ready_we = 1'h0;
if (bit_ctr_rst) begin
bit_ctr_new = 8'h0; bit_ctr_new = 8'h0;
bit_ctr_we = 1'h0; bit_ctr_we = 1'h1;
data_ready_new = 1'h0; data_ready_new = 1'h0;
data_ready_we = 1'h0; data_ready_we = 1'h1;
end
else if (bit_ctr_inc) begin
bit_ctr_new = bit_ctr_reg + 1'h1;
bit_ctr_we = 1'h1;
if (bit_ctr_rst) begin if (bit_ctr_reg == SKIP_BITS) begin
bit_ctr_new = 8'h0; data_ready_new = 1'h1;
bit_ctr_we = 1'h1; data_ready_we = 1'h1;
data_ready_new = 1'h0;
data_ready_we = 1'h1;
end
else if (bit_ctr_inc) begin
bit_ctr_new = bit_ctr_reg + 1'h1;
bit_ctr_we = 1'h1;
if (bit_ctr_reg == SKIP_BITS) begin
data_ready_new = 1'h1;
data_ready_we = 1'h1;
end
end end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// cycle_ctr_logic // cycle_ctr_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : cycle_ctr_logic
begin : cycle_ctr_logic cycle_ctr_new = cycle_ctr_reg + 1'h1;
cycle_ctr_new = cycle_ctr_reg + 1'h1; cycle_ctr_done = 1'h0;
cycle_ctr_done = 1'h0;
if (cycle_ctr_rst) begin if (cycle_ctr_rst) begin
cycle_ctr_new = 16'h0; cycle_ctr_new = 16'h0;
end
if (cycle_ctr_reg == SAMPLE_CYCLES) begin
cycle_ctr_done = 1'h1;
end
end end
if (cycle_ctr_reg == SAMPLE_CYCLES) begin
cycle_ctr_done = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// rosc_ctrl_logic // rosc_ctrl_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rosc_ctrl_logic
begin : rosc_ctrl_logic reg xor_f;
reg xor_f; reg xor_g;
reg xor_g; reg xor_sample1;
reg xor_sample1; reg xor_sample2;
reg xor_sample2;
sample1_we = 1'h0; sample1_we = 1'h0;
sample2_we = 1'h0; sample2_we = 1'h0;
entropy_we = 1'h0; entropy_we = 1'h0;
cycle_ctr_rst = 1'h0; cycle_ctr_rst = 1'h0;
bit_ctr_inc = 1'h0; bit_ctr_inc = 1'h0;
rosc_ctrl_new = CTRL_SAMPLE1; rosc_ctrl_new = CTRL_SAMPLE1;
rosc_ctrl_we = 1'h0; rosc_ctrl_we = 1'h0;
xor_f = ^f; xor_f = ^f;
xor_g = ^g; xor_g = ^g;
xor_sample1 = ^sample1_reg; xor_sample1 = ^sample1_reg;
xor_sample2 = ^sample2_reg; xor_sample2 = ^sample2_reg;
sample1_new = {sample1_reg[0], xor_f}; sample1_new = {sample1_reg[0], xor_f};
sample2_new = {sample2_reg[0], xor_g}; sample2_new = {sample2_reg[0], xor_g};
entropy_new = {entropy_reg[30 : 0], xor_sample1 ^ xor_sample2}; entropy_new = {entropy_reg[30 : 0], xor_sample1 ^ xor_sample2};
case (rosc_ctrl_reg) case (rosc_ctrl_reg)
CTRL_SAMPLE1: begin CTRL_SAMPLE1: begin
if (cycle_ctr_done) begin if (cycle_ctr_done) begin
cycle_ctr_rst = 1'h1; cycle_ctr_rst = 1'h1;
sample1_we = 1'h1; sample1_we = 1'h1;
sample2_we = 1'h1; sample2_we = 1'h1;
rosc_ctrl_new = CTRL_SAMPLE2; rosc_ctrl_new = CTRL_SAMPLE2;
rosc_ctrl_we = 1'h1; rosc_ctrl_we = 1'h1;
end end
end end
CTRL_SAMPLE2: begin CTRL_SAMPLE2: begin
if (cycle_ctr_done) begin if (cycle_ctr_done) begin
cycle_ctr_rst = 1'h1; cycle_ctr_rst = 1'h1;
sample1_we = 1'h1; sample1_we = 1'h1;
sample2_we = 1'h1; sample2_we = 1'h1;
rosc_ctrl_new = CTRL_DATA_READY; rosc_ctrl_new = CTRL_DATA_READY;
rosc_ctrl_we = 1'h1; rosc_ctrl_we = 1'h1;
end end
end end
CTRL_DATA_READY: begin CTRL_DATA_READY: begin
entropy_we = 1'h1; entropy_we = 1'h1;
bit_ctr_inc = 1'h1; bit_ctr_inc = 1'h1;
rosc_ctrl_new = CTRL_SAMPLE1; rosc_ctrl_new = CTRL_SAMPLE1;
rosc_ctrl_we = 1'h1; rosc_ctrl_we = 1'h1;
end end
default: begin default: begin
end end
endcase // case (rosc_ctrl_reg) endcase // case (rosc_ctrl_reg)
end end
endmodule // rosc endmodule // rosc
//====================================================================== //======================================================================
// EOF rosc.v // EOF rosc.v

8
hw/application_fpga/core/trng/tb/SB_LUT4.v
View File

@ -14,15 +14,15 @@
`default_nettype none `default_nettype none
module SB_LUT4 ( module SB_LUT4 (
input wire I0, input wire I0,
output wire O output wire O
); );
parameter LUT_INIT = 16'h0; parameter LUT_INIT = 16'h0;
assign O = ~I0; assign O = ~I0;
endmodule // SB_LUT4 endmodule // SB_LUT4
//====================================================================== //======================================================================
// EOF SB_LUT4.v // EOF SB_LUT4.v

174
hw/application_fpga/core/trng/tb/tb_trng.v
View File

@ -13,36 +13,36 @@
`default_nettype none `default_nettype none
module tb_trng(); module tb_trng ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 1; parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// API // API
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0; localparam STATUS_READY_BIT = 0;
localparam ADDR_ENTROPY = 8'h20; localparam ADDR_ENTROPY = 8'h20;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_monitor; reg tb_monitor;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_cs; reg tb_cs;
reg tb_we; reg tb_we;
reg [7 : 0] tb_address; reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data; reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
wire tb_ready; wire tb_ready;
@ -50,17 +50,17 @@ module tb_trng();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
rosc dut( rosc dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.cs(tb_cs), .cs(tb_cs),
.we(tb_cs), .we(tb_cs),
.address(tb_address), .address(tb_address),
.write_data(tb_write_data), .write_data(tb_write_data),
.read_data(tb_read_data), .read_data(tb_read_data),
.ready(tb_ready) .ready(tb_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -68,11 +68,10 @@ module tb_trng();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -81,15 +80,13 @@ module tb_trng();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (tb_monitor) begin
if (tb_monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -109,12 +106,12 @@ module tb_trng();
$display("Internal state:"); $display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data); $display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
$display("cycle_ctr_done: 0x%1x, cycle_ctr_rst: 0x%1x, cycle_ctr: 0x%04x", $display("cycle_ctr_done: 0x%1x, cycle_ctr_rst: 0x%1x, cycle_ctr: 0x%04x",
dut.cycle_ctr_done, dut.cycle_ctr_rst, dut.cycle_ctr_reg); dut.cycle_ctr_done, dut.cycle_ctr_rst, dut.cycle_ctr_reg);
$display("bit_ctr: 0x%02x", dut.bit_ctr_reg); $display("bit_ctr: 0x%02x", dut.bit_ctr_reg);
$display(""); $display("");
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -129,7 +126,7 @@ module tb_trng();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -139,17 +136,15 @@ module tb_trng();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("--- All %02d test cases completed successfully", tc_ctr);
$display("--- All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("--- %02d tests completed - %02d test cases did not complete successfully.",
begin tc_ctr, error_ctr);
$display("--- %02d tests completed - %02d test cases did not complete successfully.", end
tc_ctr, error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -160,19 +155,19 @@ module tb_trng();
//---------------------------------------------------------------- //----------------------------------------------------------------
task init_sim; task init_sim;
begin begin
cycle_ctr = 0; cycle_ctr = 0;
error_ctr = 0; error_ctr = 0;
tc_ctr = 0; tc_ctr = 0;
tb_monitor = 0; tb_monitor = 0;
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
tb_cs = 1'h0; tb_cs = 1'h0;
tb_cs = 1'h0; tb_cs = 1'h0;
tb_address = 8'h0; tb_address = 8'h0;
tb_write_data = 32'h0; tb_write_data = 32'h0;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -182,32 +177,32 @@ module tb_trng();
// the word read will be available in the global variable // the word read will be available in the global variable
// read_data. // read_data.
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_word(input [11 : 0] address, input [31 : 0] expected); task read_word(input [11 : 0] address, input [31 : 0] expected);
begin : read_word begin : read_word
reg [31 : 0] read_data; reg [31 : 0] read_data;
tb_address = address; tb_address = address;
tb_cs = 1'h1; tb_cs = 1'h1;
#(CLK_HALF_PERIOD); #(CLK_HALF_PERIOD);
read_data = tb_read_data; read_data = tb_read_data;
#(CLK_HALF_PERIOD); #(CLK_HALF_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
if (DEBUG) if (DEBUG) begin
begin if (read_data == expected) begin
if (read_data == expected) begin $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
read_data, address, expected);
error_ctr = error_ctr + 1;
end
$display("");
end end
else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1;
end
$display("");
end
end end
endtask // read_word endtask // read_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -224,31 +219,30 @@ module tb_trng();
$display("--- test1: completed."); $display("--- test1: completed.");
$display(""); $display("");
end end
endtask // test1 endtask // test1
//---------------------------------------------------------------- //----------------------------------------------------------------
// trng_test // trng_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : trng_test
begin : trng_test $display("");
$display(""); $display(" -= Testbench for trng started =-");
$display(" -= Testbench for trng started =-"); $display(" ============================");
$display(" ============================"); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); test1();
display_test_result(); display_test_result();
$display(""); $display("");
$display(" -= Testbench for trng completed =-"); $display(" -= Testbench for trng completed =-");
$display(" =============================="); $display(" ==============================");
$display(""); $display("");
$finish; $finish;
end // trng_test end // trng_test
endmodule // tb_trng endmodule // tb_trng
//====================================================================== //======================================================================
// EOF tb_trng.v // EOF tb_trng.v

290
hw/application_fpga/core/uart/rtl/uart.v
View File

@ -48,37 +48,37 @@
// //
//====================================================================== //======================================================================
module uart( module uart (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire rxd, input wire rxd,
output wire txd, output wire txd,
input wire cs, input wire cs,
input wire we, input wire we,
input wire [7 : 0] address, input wire [ 7 : 0] address,
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
input wire [31 : 0] write_data, input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */ /* verilator lint_on UNUSED */
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_BIT_RATE = 8'h10; localparam ADDR_BIT_RATE = 8'h10;
localparam ADDR_DATA_BITS = 8'h11; localparam ADDR_DATA_BITS = 8'h11;
localparam ADDR_STOP_BITS = 8'h12; localparam ADDR_STOP_BITS = 8'h12;
localparam ADDR_RX_STATUS = 8'h20; localparam ADDR_RX_STATUS = 8'h20;
localparam ADDR_RX_DATA = 8'h21; localparam ADDR_RX_DATA = 8'h21;
localparam ADDR_RX_BYTES = 8'h22; localparam ADDR_RX_BYTES = 8'h22;
localparam ADDR_TX_STATUS = 8'h40; localparam ADDR_TX_STATUS = 8'h40;
localparam ADDR_TX_DATA = 8'h41; localparam ADDR_TX_DATA = 8'h41;
// The default bit rate is based on target clock frequency // The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the // divided by the bit rate times in order to hit the
@ -86,7 +86,7 @@ module uart(
// Clock: 21 MHz, 62500 bps // Clock: 21 MHz, 62500 bps
// Divisor = 21E6 / 62500 = 336 // Divisor = 21E6 / 62500 = 336
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd336; localparam DEFAULT_BIT_RATE = 16'd336;
localparam DEFAULT_DATA_BITS = 4'h8; localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1; localparam DEFAULT_STOP_BITS = 2'h1;
@ -94,33 +94,33 @@ module uart(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [15 : 0] bit_rate_reg; reg [15 : 0] bit_rate_reg;
reg bit_rate_we; reg bit_rate_we;
reg [3 : 0] data_bits_reg; reg [ 3 : 0] data_bits_reg;
reg data_bits_we; reg data_bits_we;
reg [1 : 0] stop_bits_reg; reg [ 1 : 0] stop_bits_reg;
reg stop_bits_we; reg stop_bits_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
wire core_rxd_syn; wire core_rxd_syn;
wire [7 : 0] core_rxd_data; wire [ 7 : 0] core_rxd_data;
wire core_rxd_ack; wire core_rxd_ack;
reg core_txd_syn; reg core_txd_syn;
reg [7 : 0] core_txd_data; reg [ 7 : 0] core_txd_data;
wire core_txd_ready; wire core_txd_ready;
wire fifo_out_syn; wire fifo_out_syn;
wire [7 : 0] fifo_out_data; wire [ 7 : 0] fifo_out_data;
reg fifo_out_ack; reg fifo_out_ack;
wire [8 : 0] fifo_bytes; wire [ 8 : 0] fifo_bytes;
reg [31 : 0] tmp_read_data; reg [31 : 0] tmp_read_data;
reg tmp_ready; reg tmp_ready;
@ -134,45 +134,45 @@ module uart(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Module instantiations. // Module instantiations.
//---------------------------------------------------------------- //----------------------------------------------------------------
uart_core core( uart_core core (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
// Configuration parameters // Configuration parameters
.bit_rate(bit_rate_reg), .bit_rate (bit_rate_reg),
.data_bits(data_bits_reg), .data_bits(data_bits_reg),
.stop_bits(stop_bits_reg), .stop_bits(stop_bits_reg),
// External data interface // External data interface
.rxd(rxd), .rxd(rxd),
.txd(txd), .txd(txd),
// Internal receive interface. // Internal receive interface.
.rxd_syn(core_rxd_syn), .rxd_syn (core_rxd_syn),
.rxd_data(core_rxd_data), .rxd_data(core_rxd_data),
.rxd_ack(core_rxd_ack), .rxd_ack (core_rxd_ack),
// Internal transmit interface. // Internal transmit interface.
.txd_syn(core_txd_syn), .txd_syn (core_txd_syn),
.txd_data(core_txd_data), .txd_data (core_txd_data),
.txd_ready(core_txd_ready) .txd_ready(core_txd_ready)
); );
uart_fifo fifo( uart_fifo fifo (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.in_syn(core_rxd_syn), .in_syn (core_rxd_syn),
.in_data(core_rxd_data), .in_data(core_rxd_data),
.in_ack(core_rxd_ack), .in_ack (core_rxd_ack),
.fifo_bytes(fifo_bytes), .fifo_bytes(fifo_bytes),
.out_syn(fifo_out_syn), .out_syn (fifo_out_syn),
.out_data(fifo_out_data), .out_data(fifo_out_data),
.out_ack(fifo_out_ack) .out_ack (fifo_out_ack)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -182,27 +182,26 @@ module uart(
// All registers are positive edge triggered with synchronous // All registers are positive edge triggered with synchronous
// active low reset. // active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update if (!reset_n) begin
if (!reset_n) begin bit_rate_reg <= DEFAULT_BIT_RATE;
bit_rate_reg <= DEFAULT_BIT_RATE; data_bits_reg <= DEFAULT_DATA_BITS;
data_bits_reg <= DEFAULT_DATA_BITS; stop_bits_reg <= DEFAULT_STOP_BITS;
stop_bits_reg <= DEFAULT_STOP_BITS; end
else begin
if (bit_rate_we) begin
bit_rate_reg <= write_data[15 : 0];
end end
else begin
if (bit_rate_we) begin
bit_rate_reg <= write_data[15 : 0];
end
if (data_bits_we) begin if (data_bits_we) begin
data_bits_reg <= write_data[3 : 0]; data_bits_reg <= write_data[3 : 0];
end
if (stop_bits_we) begin
stop_bits_reg <= write_data[1 : 0];
end
end end
end // reg_update
if (stop_bits_we) begin
stop_bits_reg <= write_data[1 : 0];
end
end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -211,86 +210,85 @@ module uart(
// The core API that allows an internal host to control the // The core API that allows an internal host to control the
// core functionality. // core functionality.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin: api // Default assignments.
// Default assignments. bit_rate_we = 1'h0;
bit_rate_we = 1'h0; data_bits_we = 1'h0;
data_bits_we = 1'h0; stop_bits_we = 1'h0;
stop_bits_we = 1'h0; core_txd_syn = 1'h0;
core_txd_syn = 1'h0; fifo_out_ack = 1'h0;
fifo_out_ack = 1'h0; tmp_read_data = 32'h0;
tmp_read_data = 32'h0; tmp_ready = 1'h0;
tmp_ready = 1'h0;
core_txd_data = write_data[7 : 0]; core_txd_data = write_data[7 : 0];
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (we) begin if (we) begin
case (address) case (address)
ADDR_BIT_RATE: begin ADDR_BIT_RATE: begin
bit_rate_we = 1; bit_rate_we = 1;
end
ADDR_DATA_BITS: begin
data_bits_we = 1;
end
ADDR_STOP_BITS: begin
stop_bits_we = 1;
end
ADDR_TX_DATA: begin
if (core_txd_ready) begin
core_txd_syn = 1'h1;
end end
end
ADDR_DATA_BITS: begin default: begin
data_bits_we = 1; end
end endcase // case (address)
end
ADDR_STOP_BITS: begin else begin
stop_bits_we = 1; case (address)
end ADDR_BIT_RATE: begin
tmp_read_data = {16'h0, bit_rate_reg};
end
ADDR_TX_DATA: begin ADDR_DATA_BITS: begin
if (core_txd_ready) begin tmp_read_data = {28'h0, data_bits_reg};
core_txd_syn = 1'h1; end
end
end
default: begin ADDR_STOP_BITS: begin
end tmp_read_data = {30'h0, stop_bits_reg};
endcase // case (address) end
end
else begin ADDR_RX_STATUS: begin
case (address) tmp_read_data = {31'h0, fifo_out_syn};
ADDR_BIT_RATE: begin end
tmp_read_data = {16'h0, bit_rate_reg};
end
ADDR_DATA_BITS: begin ADDR_RX_DATA: begin
tmp_read_data = {28'h0, data_bits_reg}; fifo_out_ack = 1'h1;
end tmp_read_data = {24'h0, fifo_out_data};
end
ADDR_STOP_BITS: begin ADDR_RX_BYTES: begin
tmp_read_data = {30'h0, stop_bits_reg}; tmp_read_data = {23'h0, fifo_bytes};
end end
ADDR_RX_STATUS: begin ADDR_TX_STATUS: begin
tmp_read_data = {31'h0, fifo_out_syn}; tmp_read_data = {31'h0, core_txd_ready};
end end
ADDR_RX_DATA: begin default: begin
fifo_out_ack = 1'h1; end
tmp_read_data = {24'h0, fifo_out_data}; endcase // case (address)
end
ADDR_RX_BYTES: begin
tmp_read_data = {23'h0, fifo_bytes};
end
ADDR_TX_STATUS: begin
tmp_read_data = {31'h0, core_txd_ready};
end
default: begin
end
endcase // case (address)
end
end end
end end
end
endmodule // uart endmodule // uart
//====================================================================== //======================================================================
// EOF uart.v // EOF uart.v

657
hw/application_fpga/core/uart/rtl/uart_core.v
View File

@ -46,103 +46,103 @@
// //
//====================================================================== //======================================================================
module uart_core( module uart_core (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
// Configuration parameters // Configuration parameters
input wire [15 : 0] bit_rate, input wire [15 : 0] bit_rate,
input wire [3 : 0] data_bits, input wire [ 3 : 0] data_bits,
input wire [1 : 0] stop_bits, input wire [ 1 : 0] stop_bits,
// External data interface // External data interface
input wire rxd, input wire rxd,
output wire txd, output wire txd,
// Internal receive interface. // Internal receive interface.
output wire rxd_syn, output wire rxd_syn,
output wire [7 : 0] rxd_data, output wire [7 : 0] rxd_data,
input wire rxd_ack, input wire rxd_ack,
// Internal transmit interface. // Internal transmit interface.
input wire txd_syn, input wire txd_syn,
input wire [7 : 0] txd_data, input wire [7 : 0] txd_data,
output wire txd_ready output wire txd_ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter ERX_IDLE = 0; parameter ERX_IDLE = 0;
parameter ERX_START = 1; parameter ERX_START = 1;
parameter ERX_BITS = 2; parameter ERX_BITS = 2;
parameter ERX_STOP = 3; parameter ERX_STOP = 3;
parameter ERX_SYN = 4; parameter ERX_SYN = 4;
parameter ETX_IDLE = 0; parameter ETX_IDLE = 0;
parameter ETX_ACK = 1; parameter ETX_ACK = 1;
parameter ETX_START = 2; parameter ETX_START = 2;
parameter ETX_BITS = 3; parameter ETX_BITS = 3;
parameter ETX_STOP = 4; parameter ETX_STOP = 4;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg rxd0_reg; reg rxd0_reg;
reg rxd_reg; reg rxd_reg;
reg [7 : 0] rxd_byte_reg; reg [ 7 : 0] rxd_byte_reg;
reg rxd_byte_we; reg rxd_byte_we;
reg [3 : 0] rxd_bit_ctr_reg; reg [ 3 : 0] rxd_bit_ctr_reg;
reg [3 : 0] rxd_bit_ctr_new; reg [ 3 : 0] rxd_bit_ctr_new;
reg rxd_bit_ctr_we; reg rxd_bit_ctr_we;
reg rxd_bit_ctr_rst; reg rxd_bit_ctr_rst;
reg rxd_bit_ctr_inc; reg rxd_bit_ctr_inc;
reg [15 : 0] rxd_bitrate_ctr_reg; reg [15 : 0] rxd_bitrate_ctr_reg;
reg [15 : 0] rxd_bitrate_ctr_new; reg [15 : 0] rxd_bitrate_ctr_new;
reg rxd_bitrate_ctr_we; reg rxd_bitrate_ctr_we;
reg rxd_bitrate_ctr_rst; reg rxd_bitrate_ctr_rst;
reg rxd_bitrate_ctr_inc; reg rxd_bitrate_ctr_inc;
reg rxd_syn_reg; reg rxd_syn_reg;
reg rxd_syn_new; reg rxd_syn_new;
reg rxd_syn_we; reg rxd_syn_we;
reg [2 : 0] erx_ctrl_reg; reg [ 2 : 0] erx_ctrl_reg;
reg [2 : 0] erx_ctrl_new; reg [ 2 : 0] erx_ctrl_new;
reg erx_ctrl_we; reg erx_ctrl_we;
reg txd_reg; reg txd_reg;
reg txd_new; reg txd_new;
reg txd_we; reg txd_we;
reg [7 : 0] txd_byte_reg; reg [ 7 : 0] txd_byte_reg;
reg [7 : 0] txd_byte_new; reg [ 7 : 0] txd_byte_new;
reg txd_byte_we; reg txd_byte_we;
reg [3 : 0] txd_bit_ctr_reg; reg [ 3 : 0] txd_bit_ctr_reg;
reg [3 : 0] txd_bit_ctr_new; reg [ 3 : 0] txd_bit_ctr_new;
reg txd_bit_ctr_we; reg txd_bit_ctr_we;
reg txd_bit_ctr_rst; reg txd_bit_ctr_rst;
reg txd_bit_ctr_inc; reg txd_bit_ctr_inc;
reg [15 : 0] txd_bitrate_ctr_reg; reg [15 : 0] txd_bitrate_ctr_reg;
reg [15 : 0] txd_bitrate_ctr_new; reg [15 : 0] txd_bitrate_ctr_new;
reg txd_bitrate_ctr_we; reg txd_bitrate_ctr_we;
reg txd_bitrate_ctr_rst; reg txd_bitrate_ctr_rst;
reg txd_bitrate_ctr_inc; reg txd_bitrate_ctr_inc;
reg txd_ready_reg; reg txd_ready_reg;
reg txd_ready_new; reg txd_ready_new;
reg txd_ready_we; reg txd_ready_we;
reg [2 : 0] etx_ctrl_reg; reg [ 2 : 0] etx_ctrl_reg;
reg [2 : 0] etx_ctrl_new; reg [ 2 : 0] etx_ctrl_new;
reg etx_ctrl_we; reg etx_ctrl_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -154,10 +154,10 @@ module uart_core(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Concurrent connectivity for ports etc. // Concurrent connectivity for ports etc.
//---------------------------------------------------------------- //----------------------------------------------------------------
assign txd = txd_reg; assign txd = txd_reg;
assign rxd_syn = rxd_syn_reg; assign rxd_syn = rxd_syn_reg;
assign rxd_data = rxd_byte_reg; assign rxd_data = rxd_byte_reg;
assign txd_ready = txd_ready_reg; assign txd_ready = txd_ready_reg;
assign half_bit_rate = {1'b0, bit_rate[15 : 1]}; assign half_bit_rate = {1'b0, bit_rate[15 : 1]};
@ -169,74 +169,73 @@ module uart_core(
// All registers are positive edge triggered with // All registers are positive edge triggered with
// synchronous active low reset. // synchronous active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update if (!reset_n) begin
if (!reset_n) begin rxd0_reg <= 1'b0;
rxd0_reg <= 1'b0; rxd_reg <= 1'b0;
rxd_reg <= 1'b0; rxd_byte_reg <= 8'h0;
rxd_byte_reg <= 8'h0; rxd_bit_ctr_reg <= 4'h0;
rxd_bit_ctr_reg <= 4'h0; rxd_bitrate_ctr_reg <= 16'h0;
rxd_bitrate_ctr_reg <= 16'h0; rxd_syn_reg <= 0;
rxd_syn_reg <= 0; erx_ctrl_reg <= ERX_IDLE;
erx_ctrl_reg <= ERX_IDLE;
txd_reg <= 1'b1; txd_reg <= 1'b1;
txd_byte_reg <= 8'h0; txd_byte_reg <= 8'h0;
txd_bit_ctr_reg <= 4'h0; txd_bit_ctr_reg <= 4'h0;
txd_bitrate_ctr_reg <= 16'h0; txd_bitrate_ctr_reg <= 16'h0;
txd_ready_reg <= 1'b1; txd_ready_reg <= 1'b1;
etx_ctrl_reg <= ETX_IDLE; etx_ctrl_reg <= ETX_IDLE;
end
else begin
rxd0_reg <= rxd;
rxd_reg <= rxd0_reg;
if (rxd_byte_we) begin
rxd_byte_reg <= {rxd_reg, rxd_byte_reg[7 : 1]};
end end
else begin if (rxd_bit_ctr_we) begin
rxd0_reg <= rxd; rxd_bit_ctr_reg <= rxd_bit_ctr_new;
rxd_reg <= rxd0_reg;
if (rxd_byte_we) begin
rxd_byte_reg <= {rxd_reg, rxd_byte_reg[7 : 1]};
end
if (rxd_bit_ctr_we) begin
rxd_bit_ctr_reg <= rxd_bit_ctr_new;
end
if (rxd_bitrate_ctr_we) begin
rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
end
if (rxd_syn_we) begin
rxd_syn_reg <= rxd_syn_new;
end
if (erx_ctrl_we) begin
erx_ctrl_reg <= erx_ctrl_new;
end
if (txd_we) begin
txd_reg <= txd_new;
end
if (txd_byte_we) begin
txd_byte_reg <= txd_byte_new;
end
if (txd_bit_ctr_we) begin
txd_bit_ctr_reg <= txd_bit_ctr_new;
end
if (txd_bitrate_ctr_we) begin
txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
end
if (txd_ready_we) begin
txd_ready_reg <= txd_ready_new;
end
if (etx_ctrl_we) begin
etx_ctrl_reg <= etx_ctrl_new;
end
end end
end // reg_update
if (rxd_bitrate_ctr_we) begin
rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
end
if (rxd_syn_we) begin
rxd_syn_reg <= rxd_syn_new;
end
if (erx_ctrl_we) begin
erx_ctrl_reg <= erx_ctrl_new;
end
if (txd_we) begin
txd_reg <= txd_new;
end
if (txd_byte_we) begin
txd_byte_reg <= txd_byte_new;
end
if (txd_bit_ctr_we) begin
txd_bit_ctr_reg <= txd_bit_ctr_new;
end
if (txd_bitrate_ctr_we) begin
txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
end
if (txd_ready_we) begin
txd_ready_reg <= txd_ready_new;
end
if (etx_ctrl_we) begin
etx_ctrl_reg <= etx_ctrl_new;
end
end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -245,21 +244,20 @@ module uart_core(
// Bit counter for receiving data on the external // Bit counter for receiving data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rxd_bit_ctr
begin: rxd_bit_ctr rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b0;
if (rxd_bit_ctr_rst) begin
rxd_bit_ctr_new = 4'h0; rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b0; rxd_bit_ctr_we = 1'b1;
end
if (rxd_bit_ctr_rst) begin else if (rxd_bit_ctr_inc) begin
rxd_bit_ctr_new = 4'h0; rxd_bit_ctr_new = rxd_bit_ctr_reg + 1'h1;
rxd_bit_ctr_we = 1'b1; rxd_bit_ctr_we = 1'b1;
end end
end // rxd_bit_ctr
else if (rxd_bit_ctr_inc) begin
rxd_bit_ctr_new = rxd_bit_ctr_reg + 1'h1;
rxd_bit_ctr_we = 1'b1;
end
end // rxd_bit_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -268,21 +266,20 @@ module uart_core(
// Bitrate counter for receiving data on the external // Bitrate counter for receiving data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rxd_bitrate_ctr
begin: rxd_bitrate_ctr rxd_bitrate_ctr_new = 16'h0;
rxd_bitrate_ctr_we = 1'h0;
if (rxd_bitrate_ctr_rst) begin
rxd_bitrate_ctr_new = 16'h0; rxd_bitrate_ctr_new = 16'h0;
rxd_bitrate_ctr_we = 1'h0; rxd_bitrate_ctr_we = 1'b1;
end
if (rxd_bitrate_ctr_rst) begin else if (rxd_bitrate_ctr_inc) begin
rxd_bitrate_ctr_new = 16'h0; rxd_bitrate_ctr_new = rxd_bitrate_ctr_reg + 1'h1;
rxd_bitrate_ctr_we = 1'b1; rxd_bitrate_ctr_we = 1'b1;
end end
end // rxd_bitrate_ctr
else if (rxd_bitrate_ctr_inc) begin
rxd_bitrate_ctr_new = rxd_bitrate_ctr_reg + 1'h1;
rxd_bitrate_ctr_we = 1'b1;
end
end // rxd_bitrate_ctr
@ -292,21 +289,20 @@ module uart_core(
// Bit counter for transmitting data on the external // Bit counter for transmitting data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : txd_bit_ctr
begin: txd_bit_ctr txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h0;
if (txd_bit_ctr_rst) begin
txd_bit_ctr_new = 4'h0; txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h0; txd_bit_ctr_we = 1'h1;
end
if (txd_bit_ctr_rst) begin else if (txd_bit_ctr_inc) begin
txd_bit_ctr_new = 4'h0; txd_bit_ctr_new = txd_bit_ctr_reg + 1'h1;
txd_bit_ctr_we = 1'h1; txd_bit_ctr_we = 1'b1;
end end
end // txd_bit_ctr
else if (txd_bit_ctr_inc) begin
txd_bit_ctr_new = txd_bit_ctr_reg + 1'h1;
txd_bit_ctr_we = 1'b1;
end
end // txd_bit_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -315,21 +311,20 @@ module uart_core(
// Bitrate counter for transmitting data on the external // Bitrate counter for transmitting data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : txd_bitrate_ctr
begin: txd_bitrate_ctr txd_bitrate_ctr_new = 16'h0;
txd_bitrate_ctr_we = 0;
if (txd_bitrate_ctr_rst) begin
txd_bitrate_ctr_new = 16'h0; txd_bitrate_ctr_new = 16'h0;
txd_bitrate_ctr_we = 0; txd_bitrate_ctr_we = 1;
end
if (txd_bitrate_ctr_rst) begin else if (txd_bitrate_ctr_inc) begin
txd_bitrate_ctr_new = 16'h0; txd_bitrate_ctr_new = txd_bitrate_ctr_reg + 1'h1;
txd_bitrate_ctr_we = 1; txd_bitrate_ctr_we = 1;
end end
end // txd_bitrate_ctr
else if (txd_bitrate_ctr_inc) begin
txd_bitrate_ctr_new = txd_bitrate_ctr_reg + 1'h1;
txd_bitrate_ctr_we = 1;
end
end // txd_bitrate_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -340,90 +335,89 @@ module uart_core(
// if required checks parity and store correct data into // if required checks parity and store correct data into
// the rx buffer. // the rx buffer.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : external_rx_engine
begin: external_rx_engine rxd_bit_ctr_rst = 0;
rxd_bit_ctr_rst = 0; rxd_bit_ctr_inc = 0;
rxd_bit_ctr_inc = 0; rxd_bitrate_ctr_rst = 0;
rxd_bitrate_ctr_rst = 0; rxd_bitrate_ctr_inc = 0;
rxd_bitrate_ctr_inc = 0; rxd_byte_we = 0;
rxd_byte_we = 0; rxd_syn_new = 0;
rxd_syn_new = 0; rxd_syn_we = 0;
rxd_syn_we = 0; erx_ctrl_new = ERX_IDLE;
erx_ctrl_new = ERX_IDLE; erx_ctrl_we = 0;
erx_ctrl_we = 0;
case (erx_ctrl_reg) case (erx_ctrl_reg)
ERX_IDLE: begin ERX_IDLE: begin
if (!rxd_reg) begin if (!rxd_reg) begin
// Possible start bit detected. // Possible start bit detected.
rxd_bitrate_ctr_rst = 1;
erx_ctrl_new = ERX_START;
erx_ctrl_we = 1;
end
end
ERX_START: begin
rxd_bitrate_ctr_inc = 1;
if (rxd_reg) begin
// Just a glitch.
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 1;
end
else begin
if (rxd_bitrate_ctr_reg == half_bit_rate) begin
// start bit assumed. We start sampling data.
rxd_bit_ctr_rst = 1;
rxd_bitrate_ctr_rst = 1; rxd_bitrate_ctr_rst = 1;
erx_ctrl_new = ERX_START; erx_ctrl_new = ERX_BITS;
erx_ctrl_we = 1; erx_ctrl_we = 1;
end end
end end
end
ERX_START: begin
ERX_BITS: begin
if (rxd_bitrate_ctr_reg < bit_rate) begin
rxd_bitrate_ctr_inc = 1; rxd_bitrate_ctr_inc = 1;
if (rxd_reg) begin
// Just a glitch.
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 1;
end
else begin
if (rxd_bitrate_ctr_reg == half_bit_rate) begin
// start bit assumed. We start sampling data.
rxd_bit_ctr_rst = 1;
rxd_bitrate_ctr_rst = 1;
erx_ctrl_new = ERX_BITS;
erx_ctrl_we = 1;
end
end
end end
else begin
ERX_BITS: begin rxd_byte_we = 1;
if (rxd_bitrate_ctr_reg < bit_rate) begin rxd_bit_ctr_inc = 1;
rxd_bitrate_ctr_inc = 1; rxd_bitrate_ctr_rst = 1;
end if (rxd_bit_ctr_reg == (data_bits - 1)) begin
erx_ctrl_new = ERX_STOP;
else begin
rxd_byte_we = 1;
rxd_bit_ctr_inc = 1;
rxd_bitrate_ctr_rst = 1;
if (rxd_bit_ctr_reg == (data_bits - 1)) begin
erx_ctrl_new = ERX_STOP;
erx_ctrl_we = 1;
end
end
end
ERX_STOP: begin
rxd_bitrate_ctr_inc = 1;
if (rxd_bitrate_ctr_reg == bit_rate * stop_bits) begin
rxd_syn_new = 1;
rxd_syn_we = 1;
erx_ctrl_new = ERX_SYN;
erx_ctrl_we = 1; erx_ctrl_we = 1;
end end
end end
end
ERX_SYN: begin ERX_STOP: begin
if (rxd_ack) begin rxd_bitrate_ctr_inc = 1;
rxd_syn_new = 0; if (rxd_bitrate_ctr_reg == bit_rate * stop_bits) begin
rxd_syn_we = 1; rxd_syn_new = 1;
erx_ctrl_new = ERX_IDLE; rxd_syn_we = 1;
erx_ctrl_we = 1; erx_ctrl_new = ERX_SYN;
end erx_ctrl_we = 1;
end end
end
default: begin
ERX_SYN: begin
if (rxd_ack) begin
rxd_syn_new = 0;
rxd_syn_we = 1;
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 1;
end end
end
endcase // case (erx_ctrl_reg) default: begin
end // external_rx_engine end
endcase // case (erx_ctrl_reg)
end // external_rx_engine
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -432,100 +426,99 @@ module uart_core(
// Logic that implements the transmit engine towards // Logic that implements the transmit engine towards
// the external interface. // the external interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : external_tx_engine
begin: external_tx_engine txd_new = 0;
txd_new = 0; txd_we = 0;
txd_we = 0; txd_byte_new = 0;
txd_byte_new = 0; txd_byte_we = 0;
txd_byte_we = 0; txd_bit_ctr_rst = 0;
txd_bit_ctr_rst = 0; txd_bit_ctr_inc = 0;
txd_bit_ctr_inc = 0; txd_bitrate_ctr_rst = 0;
txd_bitrate_ctr_rst = 0; txd_bitrate_ctr_inc = 0;
txd_bitrate_ctr_inc = 0; txd_ready_new = 0;
txd_ready_new = 0; txd_ready_we = 0;
txd_ready_we = 0; etx_ctrl_new = ETX_IDLE;
etx_ctrl_new = ETX_IDLE; etx_ctrl_we = 0;
etx_ctrl_we = 0;
case (etx_ctrl_reg) case (etx_ctrl_reg)
ETX_IDLE: begin ETX_IDLE: begin
txd_new = 1; txd_new = 1;
txd_we = 1; txd_we = 1;
if (txd_syn) begin if (txd_syn) begin
txd_byte_new = txd_data; txd_byte_new = txd_data;
txd_byte_we = 1; txd_byte_we = 1;
txd_ready_new = 0; txd_ready_new = 0;
txd_ready_we = 1; txd_ready_we = 1;
txd_bitrate_ctr_rst = 1; txd_bitrate_ctr_rst = 1;
etx_ctrl_new = ETX_ACK; etx_ctrl_new = ETX_ACK;
etx_ctrl_we = 1; etx_ctrl_we = 1;
end end
end
ETX_ACK: begin
if (!txd_syn) begin
txd_new = 0;
txd_we = 1;
etx_ctrl_new = ETX_START;
etx_ctrl_we = 1;
end
end
ETX_START: begin
if (txd_bitrate_ctr_reg == bit_rate) begin
txd_bit_ctr_rst = 1;
etx_ctrl_new = ETX_BITS;
etx_ctrl_we = 1;
end end
else begin
txd_bitrate_ctr_inc = 1;
end
end
ETX_ACK: begin
if (!txd_syn) begin ETX_BITS: begin
txd_new = 0; if (txd_bitrate_ctr_reg < bit_rate) begin
txd_bitrate_ctr_inc = 1;
end
else begin
txd_bitrate_ctr_rst = 1;
if (txd_bit_ctr_reg == data_bits) begin
txd_new = 1;
txd_we = 1; txd_we = 1;
etx_ctrl_new = ETX_START; etx_ctrl_new = ETX_STOP;
etx_ctrl_we = 1; etx_ctrl_we = 1;
end end
end
ETX_START: begin
if (txd_bitrate_ctr_reg == bit_rate) begin
txd_bit_ctr_rst = 1;
etx_ctrl_new = ETX_BITS;
etx_ctrl_we = 1;
end
else begin else begin
txd_bitrate_ctr_inc = 1; txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
txd_we = 1;
txd_bit_ctr_inc = 1;
end end
end end
end
ETX_BITS: begin ETX_STOP: begin
if (txd_bitrate_ctr_reg < bit_rate) begin txd_bitrate_ctr_inc = 1;
txd_bitrate_ctr_inc = 1; if (txd_bitrate_ctr_reg == bit_rate * stop_bits) begin
end txd_ready_new = 1;
txd_ready_we = 1;
else begin etx_ctrl_new = ETX_IDLE;
txd_bitrate_ctr_rst = 1; etx_ctrl_we = 1;
if (txd_bit_ctr_reg == data_bits) begin
txd_new = 1;
txd_we = 1;
etx_ctrl_new = ETX_STOP;
etx_ctrl_we = 1;
end
else begin
txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
txd_we = 1;
txd_bit_ctr_inc = 1;
end
end
end end
end
default: begin
end
ETX_STOP: begin endcase // case (etx_ctrl_reg)
txd_bitrate_ctr_inc = 1; end // external_tx_engine
if (txd_bitrate_ctr_reg == bit_rate * stop_bits) begin
txd_ready_new = 1;
txd_ready_we = 1;
etx_ctrl_new = ETX_IDLE;
etx_ctrl_we = 1;
end
end
default: begin endmodule // uart
end
endcase // case (etx_ctrl_reg)
end // external_tx_engine
endmodule // uart
//====================================================================== //======================================================================
// EOF uart.v // EOF uart.v

194
hw/application_fpga/core/uart/rtl/uart_fifo.v
View File

@ -36,51 +36,51 @@
// //
//====================================================================== //======================================================================
module uart_fifo( module uart_fifo (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire in_syn, input wire in_syn,
input wire [7 : 0] in_data, input wire [7 : 0] in_data,
output wire in_ack, output wire in_ack,
output wire [8 : 0] fifo_bytes, output wire [8 : 0] fifo_bytes,
output wire out_syn, output wire out_syn,
output wire [7 : 0] out_data, output wire [7 : 0] out_data,
input wire out_ack input wire out_ack
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [7 : 0] fifo_mem [0 : 511]; reg [7 : 0] fifo_mem [0 : 511];
reg fifo_mem_we; reg fifo_mem_we;
reg [8: 0] in_ptr_reg; reg [ 8:0] in_ptr_reg;
reg [8: 0] in_ptr_new; reg [ 8:0] in_ptr_new;
reg in_ptr_we; reg in_ptr_we;
reg [8: 0] out_ptr_reg; reg [ 8:0] out_ptr_reg;
reg [8: 0] out_ptr_new; reg [ 8:0] out_ptr_new;
reg out_ptr_we; reg out_ptr_we;
reg [8: 0] byte_ctr_reg; reg [ 8:0] byte_ctr_reg;
reg [8: 0] byte_ctr_new; reg [ 8:0] byte_ctr_new;
reg byte_ctr_inc; reg byte_ctr_inc;
reg byte_ctr_dec; reg byte_ctr_dec;
reg byte_ctr_we; reg byte_ctr_we;
reg in_ack_reg; reg in_ack_reg;
reg in_ack_new; reg in_ack_new;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires // Wires
//---------------------------------------------------------------- //----------------------------------------------------------------
reg fifo_empty; reg fifo_empty;
reg fifo_full; reg fifo_full;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -95,104 +95,100 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update if (!reset_n) begin
if (!reset_n) begin in_ptr_reg <= 9'h0;
in_ptr_reg <= 9'h0; out_ptr_reg <= 9'h0;
out_ptr_reg <= 9'h0; byte_ctr_reg <= 9'h0;
byte_ctr_reg <= 9'h0; in_ack_reg <= 1'h0;
in_ack_reg <= 1'h0; end
else begin
in_ack_reg <= in_ack_new;
if (fifo_mem_we) begin
fifo_mem[in_ptr_reg] <= in_data;
end end
else begin
in_ack_reg <= in_ack_new;
if (fifo_mem_we) begin if (in_ptr_we) begin
fifo_mem[in_ptr_reg] <= in_data; in_ptr_reg <= in_ptr_new;
end
if (in_ptr_we) begin
in_ptr_reg <= in_ptr_new;
end
if (out_ptr_we) begin
out_ptr_reg <= out_ptr_new;
end
if (byte_ctr_we) begin
byte_ctr_reg <= byte_ctr_new;
end
end end
end // reg_update
if (out_ptr_we) begin
out_ptr_reg <= out_ptr_new;
end
if (byte_ctr_we) begin
byte_ctr_reg <= byte_ctr_new;
end
end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
// byte_ctr // byte_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : byte_ctr
begin : byte_ctr fifo_empty = 1'h0;
fifo_empty = 1'h0; fifo_full = 1'h0;
fifo_full = 1'h0; byte_ctr_new = 9'h0;
byte_ctr_new = 9'h0; byte_ctr_we = 1'h0;
byte_ctr_we = 1'h0;
if (byte_ctr_reg == 9'h0) begin if (byte_ctr_reg == 9'h0) begin
fifo_empty = 1'h1; fifo_empty = 1'h1;
end
if (byte_ctr_reg == 9'h1ff) begin
fifo_full = 1'h1;
end
if ((byte_ctr_inc) && (!byte_ctr_dec)) begin
byte_ctr_new = byte_ctr_reg + 1'h1;
byte_ctr_we = 1'h1;
end
else if ((!byte_ctr_inc) && (byte_ctr_dec)) begin
byte_ctr_new = byte_ctr_reg - 1'h1;
byte_ctr_we = 1'h1;
end
end end
if (byte_ctr_reg == 9'h1ff) begin
fifo_full = 1'h1;
end
if ((byte_ctr_inc) && (!byte_ctr_dec)) begin
byte_ctr_new = byte_ctr_reg + 1'h1;
byte_ctr_we = 1'h1;
end
else if ((!byte_ctr_inc) && (byte_ctr_dec)) begin
byte_ctr_new = byte_ctr_reg - 1'h1;
byte_ctr_we = 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// in_logic // in_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : in_logic
begin : in_logic fifo_mem_we = 1'h0;
fifo_mem_we = 1'h0; in_ack_new = 1'h0;
in_ack_new = 1'h0; byte_ctr_inc = 1'h0;
byte_ctr_inc = 1'h0; in_ptr_we = 1'h0;
in_ptr_we = 1'h0;
in_ptr_new = in_ptr_reg + 1'h1; in_ptr_new = in_ptr_reg + 1'h1;
if ((in_syn) && (!in_ack) && (!fifo_full)) begin if ((in_syn) && (!in_ack) && (!fifo_full)) begin
fifo_mem_we = 1'h1; fifo_mem_we = 1'h1;
in_ack_new = 1'h1; in_ack_new = 1'h1;
byte_ctr_inc = 1'h1; byte_ctr_inc = 1'h1;
in_ptr_we = 1'h1; in_ptr_we = 1'h1;
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// out_logic // out_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : out_logic
begin : out_logic byte_ctr_dec = 1'h0;
byte_ctr_dec = 1'h0; out_ptr_we = 1'h0;
out_ptr_we = 1'h0;
out_ptr_new = out_ptr_reg + 1'h1; out_ptr_new = out_ptr_reg + 1'h1;
if ((out_ack) && (!fifo_empty)) begin if ((out_ack) && (!fifo_empty)) begin
byte_ctr_dec = 1'h1; byte_ctr_dec = 1'h1;
out_ptr_we = 1'h1; out_ptr_we = 1'h1;
end
end end
end
endmodule // uart_fifo endmodule // uart_fifo
//====================================================================== //======================================================================
// EOF uart_fifo.v // EOF uart_fifo.v

208
hw/application_fpga/core/uart/tb/tb_uart.v
View File

@ -36,24 +36,24 @@
// //
//====================================================================== //======================================================================
module tb_uart(); module tb_uart ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 0; parameter DEBUG = 0;
parameter VERBOSE = 0; parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2; parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
@ -61,32 +61,32 @@ module tb_uart();
wire tb_txd; wire tb_txd;
reg tb_cs; reg tb_cs;
reg tb_we; reg tb_we;
reg [7 : 0] tb_address; reg [ 7 : 0] tb_address;
reg [31 : 0] tb_write_data; reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
wire tb_ready; wire tb_ready;
reg txd_state; reg txd_state;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
uart dut( uart dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.rxd(tb_rxd), .rxd(tb_rxd),
.txd(tb_txd), .txd(tb_txd),
// API interface. // API interface.
.cs(tb_cs), .cs(tb_cs),
.we(tb_we), .we(tb_we),
.address(tb_address), .address(tb_address),
.write_data(tb_write_data), .write_data(tb_write_data),
.read_data(tb_read_data), .read_data(tb_read_data),
.ready(tb_ready) .ready(tb_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -99,30 +99,26 @@ module tb_uart();
// //
// Clock generator process. // Clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk;
#CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
// sys_monitor // sys_monitor
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor #(CLK_PERIOD);
#(CLK_PERIOD); if (DEBUG) begin
if (DEBUG) dump_rx_state();
begin dump_tx_state();
dump_rx_state(); $display("");
dump_tx_state();
$display("");
end
if (VERBOSE)
begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end end
if (VERBOSE) begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -130,21 +126,18 @@ module tb_uart();
// //
// Observes what happens on the dut tx port and reports it. // Observes what happens on the dut tx port and reports it.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : tx_monitor
begin : tx_monitor if ((!tb_txd) && txd_state) begin
if ((!tb_txd) && txd_state) $display("txd going low.");
begin txd_state = 0;
$display("txd going low.");
txd_state = 0;
end
if (tb_txd && (!txd_state))
begin
$display("txd going high");
txd_state = 1;
end
end end
if (tb_txd && (!txd_state)) begin
$display("txd going high");
txd_state = 1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// dump_dut_state() // dump_dut_state()
@ -156,27 +149,24 @@ module tb_uart();
$display("State of DUT"); $display("State of DUT");
$display("------------"); $display("------------");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("rxd = 0x%01x, txd = 0x%01x,", $display("rxd = 0x%01x, txd = 0x%01x,", dut.core.rxd, dut.core.txd);
dut.core.rxd, dut.core.txd);
$display(""); $display("");
$display("Sample and data registers:"); $display("Sample and data registers:");
$display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x", $display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x", dut.core.rxd_reg, dut.core.rxd_byte_reg);
dut.core.rxd_reg, dut.core.rxd_byte_reg);
$display(""); $display("");
$display("Counters:"); $display("Counters:");
$display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x", $display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x", dut.core.rxd_bit_ctr_reg,
dut.core.rxd_bit_ctr_reg, dut.core.rxd_bitrate_ctr_reg); dut.core.rxd_bitrate_ctr_reg);
$display(""); $display("");
$display("Control signals and FSM state:"); $display("Control signals and FSM state:");
$display("erx_ctrl_reg = 0x%02x", $display("erx_ctrl_reg = 0x%02x", dut.core.erx_ctrl_reg);
dut.core.erx_ctrl_reg);
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
@ -187,11 +177,12 @@ module tb_uart();
//---------------------------------------------------------------- //----------------------------------------------------------------
task dump_rx_state; task dump_rx_state;
begin begin
$display("rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x", $display(
dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg, "rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x",
dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg); dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg,
dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg);
end end
endtask // dump_dut_state endtask // dump_dut_state
@ -203,7 +194,7 @@ module tb_uart();
task dump_tx_state; task dump_tx_state;
begin begin
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -216,7 +207,7 @@ module tb_uart();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -241,7 +232,7 @@ module tb_uart();
txd_state = 1; txd_state = 1;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -262,12 +253,11 @@ module tb_uart();
#(CLK_PERIOD * dut.DEFAULT_BIT_RATE); #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
// Send the bits LSB first. // Send the bits LSB first.
for (i = 0 ; i < 8 ; i = i + 1) for (i = 0; i < 8; i = i + 1) begin
begin $display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]); tb_rxd = data[i];
tb_rxd = data[i]; #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
#(CLK_PERIOD * dut.DEFAULT_BIT_RATE); end
end
// Send two stop bits. I.e. two bit times high (mark) value. // Send two stop bits. I.e. two bit times high (mark) value.
$display("*** Transmitting two stop bits."); $display("*** Transmitting two stop bits.");
@ -275,7 +265,7 @@ module tb_uart();
#(2 * CLK_PERIOD * dut.DEFAULT_BIT_RATE * dut.DEFAULT_STOP_BITS); #(2 * CLK_PERIOD * dut.DEFAULT_BIT_RATE * dut.DEFAULT_STOP_BITS);
$display("*** End of transmission."); $display("*** End of transmission.");
end end
endtask // transmit_byte endtask // transmit_byte
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -290,19 +280,16 @@ module tb_uart();
transmit_byte(data); transmit_byte(data);
if (dut.core.rxd_byte_reg == data) if (dut.core.rxd_byte_reg == data) begin
begin $display("*** Correct data: 0x%01x captured by the dut.", dut.core.rxd_byte_reg);
$display("*** Correct data: 0x%01x captured by the dut.", end
dut.core.rxd_byte_reg); else begin
end $display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
else dut.core.rxd_byte_reg, data);
begin error_ctr = error_ctr + 1;
$display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.", end
dut.core.rxd_byte_reg, data);
error_ctr = error_ctr + 1;
end
end end
endtask // check_transmit endtask // check_transmit
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -317,7 +304,7 @@ module tb_uart();
check_transmit(8'hde); check_transmit(8'hde);
check_transmit(8'had); check_transmit(8'had);
end end
endtask // test_transmit endtask // test_transmit
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -327,38 +314,35 @@ module tb_uart();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("*** All %02d test cases completed successfully", tc_ctr);
$display("*** All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("*** %02d test cases did not complete successfully.", error_ctr);
begin end
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
// uart_test // uart_test
// The main test functionality. // The main test functionality.
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : uart_test
begin : uart_test $display(" -- Testbench for uart core started --");
$display(" -- Testbench for uart core started --");
init_sim(); init_sim();
dump_dut_state(); dump_dut_state();
reset_dut(); reset_dut();
dump_dut_state(); dump_dut_state();
test_transmit(); test_transmit();
display_test_result(); display_test_result();
$display("*** Simulation done."); $display("*** Simulation done.");
$finish; $finish;
end // uart_test end // uart_test
endmodule // tb_uart endmodule // tb_uart
//====================================================================== //======================================================================
// EOF tb_uart.v // EOF tb_uart.v

76
hw/application_fpga/core/uds/rtl/uds.v
View File

@ -13,23 +13,23 @@
`default_nettype none `default_nettype none
module uds( module uds (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire fw_app_mode, input wire fw_app_mode,
input wire cs, input wire cs,
input wire [2 : 0] address, input wire [ 2 : 0] address,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
output wire ready output wire ready
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg uds_rd_reg [0 : 7]; reg uds_rd_reg [0 : 7];
reg uds_rd_we; reg uds_rd_we;
@ -50,32 +50,31 @@ module uds(
//---------------------------------------------------------------- //----------------------------------------------------------------
// uds rom instance. // uds rom instance.
//---------------------------------------------------------------- //----------------------------------------------------------------
uds_rom rom_i( uds_rom rom_i (
.addr(address), .addr(address),
.re(uds_rd_we), .re (uds_rd_we),
.data(tmp_read_data) .data(tmp_read_data)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update integer i;
integer i;
if (!reset_n) begin if (!reset_n) begin
for (i = 0 ; i < 8 ; i = i + 1) begin for (i = 0; i < 8; i = i + 1) begin
uds_rd_reg[i] <= 1'h0;; uds_rd_reg[i] <= 1'h0;
end
end end
else begin end
if (uds_rd_we) begin else begin
uds_rd_reg[address[2 : 0]] <= 1'h1; if (uds_rd_we) begin
end uds_rd_reg[address[2 : 0]] <= 1'h1;
end end
end // reg_update end
end // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -83,22 +82,21 @@ module uds(
// //
// The interface command decoding logic. // The interface command decoding logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api uds_rd_we = 1'h0;
uds_rd_we = 1'h0; tmp_ready = 1'h0;
tmp_ready = 1'h0;
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (!fw_app_mode) begin if (!fw_app_mode) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
uds_rd_we = 1'h1; uds_rd_we = 1'h1;
end end
end
end end
end end
endmodule // uds end
endmodule // uds
//====================================================================== //======================================================================
// EOF uds.v // EOF uds.v

26
hw/application_fpga/core/uds/rtl/uds_rom.v
View File

@ -14,25 +14,27 @@
`default_nettype none `default_nettype none
module uds_rom( module uds_rom (
input wire [2:0] addr, input wire [2:0] addr,
input wire re, input wire re,
output wire [31:0] data output wire [31:0] data
); );
generate generate
genvar ii; genvar ii;
for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts
(* uds_rom_idx=ii, keep *) SB_LUT4 (* uds_rom_idx=ii, keep *) SB_LUT4 #(
#( .LUT_INIT({8'ha6 ^ ii[7:0], 8'h00})
.LUT_INIT({8'ha6 ^ ii[7:0], 8'h00})
) lut_i ( ) lut_i (
.I0(addr[0]), .I1(addr[1]), .I2(addr[2]), .I3(re), .I0(addr[0]),
.O(data[ii]) .I1(addr[1]),
.I2(addr[2]),
.I3(re),
.O (data[ii])
); );
end end
endgenerate endgenerate
endmodule // uds_rom endmodule // uds_rom
//====================================================================== //======================================================================
// EOF uds_rom.v // EOF uds_rom.v

155
hw/application_fpga/core/uds/tb/tb_uds.v
View File

@ -13,49 +13,49 @@
`default_nettype none `default_nettype none
module tb_uds(); module tb_uds ();
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
parameter DEBUG = 1; parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1; parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_UDS_FIRST = 8'h10; localparam ADDR_UDS_FIRST = 8'h10;
localparam ADDR_UDS_LAST = 8'h17; localparam ADDR_UDS_LAST = 8'h17;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Register and Wire declarations. // Register and Wire declarations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] cycle_ctr; reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr; reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr; reg [31 : 0] tc_ctr;
reg tb_monitor; reg tb_monitor;
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_fw_app_mode; reg tb_fw_app_mode;
reg tb_cs; reg tb_cs;
reg [7 : 0] tb_address; reg [ 7 : 0] tb_address;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
uds dut( uds dut (
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.fw_app_mode(tb_fw_app_mode), .fw_app_mode(tb_fw_app_mode),
.cs(tb_cs), .cs(tb_cs),
.address(tb_address), .address(tb_address),
.read_data(tb_read_data) .read_data(tb_read_data)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -63,11 +63,10 @@ module tb_uds();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen #CLK_HALF_PERIOD;
#CLK_HALF_PERIOD; tb_clk = !tb_clk;
tb_clk = !tb_clk; end // clk_gen
end // clk_gen
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -76,15 +75,13 @@ module tb_uds();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor cycle_ctr = cycle_ctr + 1;
cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD);
#(CLK_PERIOD); if (tb_monitor) begin
if (tb_monitor) dump_dut_state();
begin
dump_dut_state();
end
end end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -104,14 +101,15 @@ module tb_uds();
$display("Internal state:"); $display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data); $display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
for (i = 0 ; i < 8 ; i = i + 1) begin for (i = 0; i < 8; i = i + 1) begin
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]); $display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i,
dut.uds_rd_reg[i]);
end end
$display(""); $display("");
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -126,7 +124,7 @@ module tb_uds();
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
tb_reset_n = 1; tb_reset_n = 1;
end end
endtask // reset_dut endtask // reset_dut
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -136,17 +134,15 @@ module tb_uds();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin $display("--- All %02d test cases completed successfully", tc_ctr);
$display("--- All %02d test cases completed successfully", tc_ctr); end
end else begin
else $display("--- %02d tests completed - %02d test cases did not complete successfully.",
begin tc_ctr, error_ctr);
$display("--- %02d tests completed - %02d test cases did not complete successfully.", end
tc_ctr, error_ctr);
end
end end
endtask // display_test_result endtask // display_test_result
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -157,10 +153,10 @@ module tb_uds();
//---------------------------------------------------------------- //----------------------------------------------------------------
task init_sim; task init_sim;
begin begin
cycle_ctr = 0; cycle_ctr = 0;
error_ctr = 0; error_ctr = 0;
tc_ctr = 0; tc_ctr = 0;
tb_monitor = 0; tb_monitor = 0;
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
@ -168,7 +164,7 @@ module tb_uds();
tb_cs = 1'h0; tb_cs = 1'h0;
tb_address = 8'h0; tb_address = 8'h0;
end end
endtask // init_sim endtask // init_sim
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -178,32 +174,32 @@ module tb_uds();
// the word read will be available in the global variable // the word read will be available in the global variable
// read_data. // read_data.
//---------------------------------------------------------------- //----------------------------------------------------------------
task read_word(input [11 : 0] address, input [31 : 0] expected); task read_word(input [11 : 0] address, input [31 : 0] expected);
begin : read_word begin : read_word
reg [31 : 0] read_data; reg [31 : 0] read_data;
tb_address = address; tb_address = address;
tb_cs = 1'h1; tb_cs = 1'h1;
#(CLK_HALF_PERIOD); #(CLK_HALF_PERIOD);
read_data = tb_read_data; read_data = tb_read_data;
#(CLK_HALF_PERIOD); #(CLK_HALF_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
if (DEBUG) if (DEBUG) begin
begin if (read_data == expected) begin
if (read_data == expected) begin $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
read_data, address, expected);
error_ctr = error_ctr + 1;
end
$display("");
end end
else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1;
end
$display("");
end
end end
endtask // read_word endtask // read_word
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -300,31 +296,30 @@ module tb_uds();
$display("--- test1: completed."); $display("--- test1: completed.");
$display(""); $display("");
end end
endtask // test1 endtask // test1
//---------------------------------------------------------------- //----------------------------------------------------------------
// uds_test // uds_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : uds_test
begin : uds_test $display("");
$display(""); $display(" -= Testbench for uds started =-");
$display(" -= Testbench for uds started =-"); $display(" ===========================");
$display(" ==========================="); $display("");
$display("");
init_sim(); init_sim();
reset_dut(); reset_dut();
test1(); test1();
display_test_result(); display_test_result();
$display(""); $display("");
$display(" -= Testbench for uds completed =-"); $display(" -= Testbench for uds completed =-");
$display(" ============================="); $display(" =============================");
$display(""); $display("");
$finish; $finish;
end // uds_test end // uds_test
endmodule // tb_uds endmodule // tb_uds
//====================================================================== //======================================================================
// EOF tb_uds.v // EOF tb_uds.v

643
hw/application_fpga/rtl/application_fpga.v
View File

@ -16,45 +16,45 @@
`default_nettype none `default_nettype none
module application_fpga( module application_fpga (
output wire interface_rx, output wire interface_rx,
input wire interface_tx, input wire interface_tx,
output wire spi_ss, output wire spi_ss,
output wire spi_sck, output wire spi_sck,
output wire spi_mosi, output wire spi_mosi,
input wire spi_miso, input wire spi_miso,
input wire touch_event, input wire touch_event,
input wire app_gpio1, input wire app_gpio1,
input wire app_gpio2, input wire app_gpio2,
output wire app_gpio3, output wire app_gpio3,
output wire app_gpio4, output wire app_gpio4,
output wire led_r, output wire led_r,
output wire led_g, output wire led_g,
output wire led_b output wire led_b
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Local parameters // Local parameters
//---------------------------------------------------------------- //----------------------------------------------------------------
// Top level mem area prefixes. // Top level mem area prefixes.
localparam ROM_PREFIX = 2'h0; localparam ROM_PREFIX = 2'h0;
localparam RAM_PREFIX = 2'h1; localparam RAM_PREFIX = 2'h1;
localparam RESERVED_PREFIX = 2'h2; localparam RESERVED_PREFIX = 2'h2;
localparam MMIO_PREFIX = 2'h3; localparam MMIO_PREFIX = 2'h3;
// MMIO core sub-prefixes. // MMIO core sub-prefixes.
localparam TRNG_PREFIX = 6'h00; localparam TRNG_PREFIX = 6'h00;
localparam TIMER_PREFIX = 6'h01; localparam TIMER_PREFIX = 6'h01;
localparam UDS_PREFIX = 6'h02; localparam UDS_PREFIX = 6'h02;
localparam UART_PREFIX = 6'h03; localparam UART_PREFIX = 6'h03;
localparam TOUCH_SENSE_PREFIX = 6'h04; localparam TOUCH_SENSE_PREFIX = 6'h04;
localparam FW_RAM_PREFIX = 6'h10; localparam FW_RAM_PREFIX = 6'h10;
localparam TK1_PREFIX = 6'h3f; localparam TK1_PREFIX = 6'h3f;
// Instruction used to cause a trap. // Instruction used to cause a trap.
localparam ILLEGAL_INSTRUCTION = 32'h0; localparam ILLEGAL_INSTRUCTION = 32'h0;
@ -63,11 +63,11 @@ module application_fpga(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers, memories with associated wires. // Registers, memories with associated wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] muxed_rdata_reg; reg [31 : 0] muxed_rdata_reg;
reg [31 : 0] muxed_rdata_new; reg [31 : 0] muxed_rdata_new;
reg muxed_ready_reg; reg muxed_ready_reg;
reg muxed_ready_new; reg muxed_ready_new;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -91,7 +91,7 @@ module application_fpga(
wire rom_ready; wire rom_ready;
reg ram_cs; reg ram_cs;
reg [3 : 0] ram_we; reg [ 3 : 0] ram_we;
reg [15 : 0] ram_address; reg [15 : 0] ram_address;
reg [31 : 0] ram_write_data; reg [31 : 0] ram_write_data;
wire [31 : 0] ram_read_data; wire [31 : 0] ram_read_data;
@ -99,47 +99,47 @@ module application_fpga(
reg trng_cs; reg trng_cs;
reg trng_we; reg trng_we;
reg [7 : 0] trng_address; reg [ 7 : 0] trng_address;
reg [31 : 0] trng_write_data; reg [31 : 0] trng_write_data;
wire [31 : 0] trng_read_data; wire [31 : 0] trng_read_data;
wire trng_ready; wire trng_ready;
reg timer_cs; reg timer_cs;
reg timer_we; reg timer_we;
reg [7 : 0] timer_address; reg [ 7 : 0] timer_address;
reg [31 : 0] timer_write_data; reg [31 : 0] timer_write_data;
wire [31 : 0] timer_read_data; wire [31 : 0] timer_read_data;
wire timer_ready; wire timer_ready;
reg uds_cs; reg uds_cs;
reg [2 : 0] uds_address; reg [ 2 : 0] uds_address;
wire [31 : 0] uds_read_data; wire [31 : 0] uds_read_data;
wire uds_ready; wire uds_ready;
reg uart_cs; reg uart_cs;
reg uart_we; reg uart_we;
reg [7 : 0] uart_address; reg [ 7 : 0] uart_address;
reg [31 : 0] uart_write_data; reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data; wire [31 : 0] uart_read_data;
wire uart_ready; wire uart_ready;
reg fw_ram_cs; reg fw_ram_cs;
reg [3 : 0] fw_ram_we; reg [ 3 : 0] fw_ram_we;
reg [8 : 0] fw_ram_address; reg [ 8 : 0] fw_ram_address;
reg [31 : 0] fw_ram_write_data; reg [31 : 0] fw_ram_write_data;
wire [31 : 0] fw_ram_read_data; wire [31 : 0] fw_ram_read_data;
wire fw_ram_ready; wire fw_ram_ready;
reg touch_sense_cs; reg touch_sense_cs;
reg touch_sense_we; reg touch_sense_we;
reg [7 : 0] touch_sense_address; reg [ 7 : 0] touch_sense_address;
wire [31 : 0] touch_sense_read_data; wire [31 : 0] touch_sense_read_data;
wire touch_sense_ready; wire touch_sense_ready;
reg tk1_cs; reg tk1_cs;
reg tk1_we; reg tk1_we;
reg [7 : 0] tk1_address; reg [ 7 : 0] tk1_address;
reg [31 : 0] tk1_write_data; reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire fw_app_mode; wire fw_app_mode;
@ -153,371 +153,370 @@ module application_fpga(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Module instantiations. // Module instantiations.
//---------------------------------------------------------------- //----------------------------------------------------------------
clk_reset_gen #(.RESET_CYCLES(200)) clk_reset_gen #(
reset_gen_inst( .RESET_CYCLES(200)
.sys_reset(tk1_system_reset), ) reset_gen_inst (
.clk(clk), .sys_reset(tk1_system_reset),
.rst_n(reset_n) .clk(clk),
); .rst_n(reset_n)
);
picorv32 #( picorv32 #(
.ENABLE_COUNTERS(0), .ENABLE_COUNTERS(0),
.TWO_STAGE_SHIFT(0), .TWO_STAGE_SHIFT(0),
.CATCH_MISALIGN(0), .CATCH_MISALIGN (0),
.COMPRESSED_ISA(1), .COMPRESSED_ISA (1),
.ENABLE_FAST_MUL(1), .ENABLE_FAST_MUL(1),
.BARREL_SHIFTER(1) .BARREL_SHIFTER (1)
) cpu( ) cpu (
.clk(clk), .clk(clk),
.resetn(reset_n), .resetn(reset_n),
.trap(cpu_trap), .trap(cpu_trap),
.mem_valid(cpu_valid), .mem_valid(cpu_valid),
.mem_ready(muxed_ready_reg), .mem_ready(muxed_ready_reg),
.mem_addr (cpu_addr), .mem_addr (cpu_addr),
.mem_wdata(cpu_wdata), .mem_wdata(cpu_wdata),
.mem_wstrb(cpu_wstrb), .mem_wstrb(cpu_wstrb),
.mem_rdata(muxed_rdata_reg), .mem_rdata(muxed_rdata_reg),
.mem_instr(cpu_instr), .mem_instr(cpu_instr),
// Defined unused ports. Makes lint happy. But // Defined unused ports. Makes lint happy. But
// we still needs to help lint with empty ports. // we still needs to help lint with empty ports.
/* verilator lint_off PINCONNECTEMPTY */ /* verilator lint_off PINCONNECTEMPTY */
.irq(32'h0), .irq(32'h0),
.eoi(), .eoi(),
.trace_valid(), .trace_valid(),
.trace_data(), .trace_data(),
.mem_la_read(), .mem_la_read(),
.mem_la_write(), .mem_la_write(),
.mem_la_addr(), .mem_la_addr(),
.mem_la_wdata(), .mem_la_wdata(),
.mem_la_wstrb(), .mem_la_wstrb(),
.pcpi_valid(), .pcpi_valid(),
.pcpi_insn(), .pcpi_insn(),
.pcpi_rs1(), .pcpi_rs1(),
.pcpi_rs2(), .pcpi_rs2(),
.pcpi_wr(1'h0), .pcpi_wr(1'h0),
.pcpi_rd(32'h0), .pcpi_rd(32'h0),
.pcpi_wait(1'h0), .pcpi_wait(1'h0),
.pcpi_ready(1'h0) .pcpi_ready(1'h0)
/* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_on PINCONNECTEMPTY */
); );
rom rom_inst( rom rom_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cs(rom_cs), .cs(rom_cs),
.address(rom_address), .address(rom_address),
.read_data(rom_read_data), .read_data(rom_read_data),
.ready(rom_ready) .ready(rom_ready)
); );
ram ram_inst( ram ram_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.ram_addr_rand(ram_addr_rand), .ram_addr_rand(ram_addr_rand),
.ram_data_rand(ram_data_rand), .ram_data_rand(ram_data_rand),
.cs(ram_cs), .cs(ram_cs),
.we(ram_we), .we(ram_we),
.address(ram_address), .address(ram_address),
.write_data(ram_write_data), .write_data(ram_write_data),
.read_data(ram_read_data), .read_data(ram_read_data),
.ready(ram_ready) .ready(ram_ready)
); );
fw_ram fw_ram_inst( fw_ram fw_ram_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .fw_app_mode(fw_app_mode),
.cs(fw_ram_cs), .cs(fw_ram_cs),
.we(fw_ram_we), .we(fw_ram_we),
.address(fw_ram_address), .address(fw_ram_address),
.write_data(fw_ram_write_data), .write_data(fw_ram_write_data),
.read_data(fw_ram_read_data), .read_data(fw_ram_read_data),
.ready(fw_ram_ready) .ready(fw_ram_ready)
); );
rosc trng_inst( rosc trng_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cs(trng_cs), .cs(trng_cs),
.we(trng_we), .we(trng_we),
.address(trng_address), .address(trng_address),
.write_data(trng_write_data), .write_data(trng_write_data),
.read_data(trng_read_data), .read_data(trng_read_data),
.ready(trng_ready) .ready(trng_ready)
); );
timer timer_inst( timer timer_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cs(timer_cs), .cs(timer_cs),
.we(timer_we), .we(timer_we),
.address(timer_address), .address(timer_address),
.write_data(timer_write_data), .write_data(timer_write_data),
.read_data(timer_read_data), .read_data(timer_read_data),
.ready(timer_ready) .ready(timer_ready)
); );
uds uds_inst( uds uds_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .fw_app_mode(fw_app_mode),
.cs(uds_cs), .cs(uds_cs),
.address(uds_address), .address(uds_address),
.read_data(uds_read_data), .read_data(uds_read_data),
.ready(uds_ready) .ready(uds_ready)
); );
uart uart_inst( uart uart_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.rxd(interface_tx), .rxd(interface_tx),
.txd(interface_rx), .txd(interface_rx),
.cs(uart_cs), .cs(uart_cs),
.we(uart_we), .we(uart_we),
.address(uart_address), .address(uart_address),
.write_data(uart_write_data), .write_data(uart_write_data),
.read_data(uart_read_data), .read_data(uart_read_data),
.ready(uart_ready) .ready(uart_ready)
); );
touch_sense touch_sense_inst( touch_sense touch_sense_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.touch_event(touch_event), .touch_event(touch_event),
.cs(touch_sense_cs), .cs(touch_sense_cs),
.we(touch_sense_we), .we(touch_sense_we),
.address(touch_sense_address), .address(touch_sense_address),
.read_data(touch_sense_read_data), .read_data(touch_sense_read_data),
.ready(touch_sense_ready) .ready(touch_sense_ready)
); );
tk1 tk1_inst( tk1 tk1_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .fw_app_mode(fw_app_mode),
.cpu_addr(cpu_addr), .cpu_addr (cpu_addr),
.cpu_instr(cpu_instr), .cpu_instr (cpu_instr),
.cpu_valid(cpu_valid), .cpu_valid (cpu_valid),
.cpu_trap(cpu_trap), .cpu_trap (cpu_trap),
.force_trap(force_trap), .force_trap(force_trap),
.system_reset(tk1_system_reset), .system_reset(tk1_system_reset),
.ram_addr_rand(ram_addr_rand), .ram_addr_rand(ram_addr_rand),
.ram_data_rand(ram_data_rand), .ram_data_rand(ram_data_rand),
.spi_ss(spi_ss), .spi_ss (spi_ss),
.spi_sck(spi_sck), .spi_sck (spi_sck),
.spi_mosi(spi_mosi), .spi_mosi(spi_mosi),
.spi_miso(spi_miso), .spi_miso(spi_miso),
.led_r(led_r), .led_r(led_r),
.led_g(led_g), .led_g(led_g),
.led_b(led_b), .led_b(led_b),
.gpio1(app_gpio1), .gpio1(app_gpio1),
.gpio2(app_gpio2), .gpio2(app_gpio2),
.gpio3(app_gpio3), .gpio3(app_gpio3),
.gpio4(app_gpio4), .gpio4(app_gpio4),
.cs(tk1_cs), .cs(tk1_cs),
.we(tk1_we), .we(tk1_we),
.address(tk1_address), .address(tk1_address),
.write_data(tk1_write_data), .write_data(tk1_write_data),
.read_data(tk1_read_data), .read_data(tk1_read_data),
.ready(tk1_ready) .ready(tk1_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Reg_update. // Reg_update.
// Posedge triggered with synchronous, active low reset. // Posedge triggered with synchronous, active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin muxed_rdata_reg <= 32'h0;
muxed_rdata_reg <= 32'h0; muxed_ready_reg <= 1'h0;
muxed_ready_reg <= 1'h0;
end
else begin
muxed_rdata_reg <= muxed_rdata_new;
muxed_ready_reg <= muxed_ready_new;
end
end end
else begin
muxed_rdata_reg <= muxed_rdata_new;
muxed_ready_reg <= muxed_ready_new;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// cpu_mem_ctrl // cpu_mem_ctrl
// CPU memory decode and control logic. // CPU memory decode and control logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : cpu_mem_ctrl
begin : cpu_mem_ctrl reg [1 : 0] area_prefix;
reg [1 : 0] area_prefix; reg [5 : 0] core_prefix;
reg [5 : 0] core_prefix;
area_prefix = cpu_addr[31 : 30]; area_prefix = cpu_addr[31 : 30];
core_prefix = cpu_addr[29 : 24]; core_prefix = cpu_addr[29 : 24];
muxed_ready_new = 1'h0; muxed_ready_new = 1'h0;
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
rom_cs = 1'h0; rom_cs = 1'h0;
rom_address = cpu_addr[13 : 2]; rom_address = cpu_addr[13 : 2];
ram_cs = 1'h0; ram_cs = 1'h0;
ram_we = 4'h0; ram_we = 4'h0;
ram_address = cpu_addr[17 : 2]; ram_address = cpu_addr[17 : 2];
ram_write_data = cpu_wdata; ram_write_data = cpu_wdata;
fw_ram_cs = 1'h0; fw_ram_cs = 1'h0;
fw_ram_we = cpu_wstrb; fw_ram_we = cpu_wstrb;
fw_ram_address = cpu_addr[10 : 2]; fw_ram_address = cpu_addr[10 : 2];
fw_ram_write_data = cpu_wdata; fw_ram_write_data = cpu_wdata;
trng_cs = 1'h0; trng_cs = 1'h0;
trng_we = |cpu_wstrb; trng_we = |cpu_wstrb;
trng_address = cpu_addr[9 : 2]; trng_address = cpu_addr[9 : 2];
trng_write_data = cpu_wdata; trng_write_data = cpu_wdata;
timer_cs = 1'h0; timer_cs = 1'h0;
timer_we = |cpu_wstrb; timer_we = |cpu_wstrb;
timer_address = cpu_addr[9 : 2]; timer_address = cpu_addr[9 : 2];
timer_write_data = cpu_wdata; timer_write_data = cpu_wdata;
uds_cs = 1'h0; uds_cs = 1'h0;
uds_address = cpu_addr[4 : 2]; uds_address = cpu_addr[4 : 2];
uart_cs = 1'h0; uart_cs = 1'h0;
uart_we = |cpu_wstrb; uart_we = |cpu_wstrb;
uart_address = cpu_addr[9 : 2]; uart_address = cpu_addr[9 : 2];
uart_write_data = cpu_wdata; uart_write_data = cpu_wdata;
touch_sense_cs = 1'h0; touch_sense_cs = 1'h0;
touch_sense_we = |cpu_wstrb; touch_sense_we = |cpu_wstrb;
touch_sense_address = cpu_addr[9 : 2]; touch_sense_address = cpu_addr[9 : 2];
tk1_cs = 1'h0; tk1_cs = 1'h0;
tk1_we = |cpu_wstrb; tk1_we = |cpu_wstrb;
tk1_address = cpu_addr[9 : 2]; tk1_address = cpu_addr[9 : 2];
tk1_write_data = cpu_wdata; tk1_write_data = cpu_wdata;
// Two stage mux implementing read and // Two stage mux implementing read and
// write access performed based on the address // write access performed based on the address
// from the CPU. // from the CPU.
if (cpu_valid && !muxed_ready_reg) begin if (cpu_valid && !muxed_ready_reg) begin
if (force_trap) begin if (force_trap) begin
muxed_rdata_new = ILLEGAL_INSTRUCTION; muxed_rdata_new = ILLEGAL_INSTRUCTION;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
else begin else begin
case (area_prefix) case (area_prefix)
ROM_PREFIX: begin ROM_PREFIX: begin
rom_cs = 1'h1; rom_cs = 1'h1;
muxed_rdata_new = rom_read_data; muxed_rdata_new = rom_read_data;
muxed_ready_new = rom_ready; muxed_ready_new = rom_ready;
end end
RAM_PREFIX: begin RAM_PREFIX: begin
ram_cs = 1'h1; ram_cs = 1'h1;
ram_we = cpu_wstrb; ram_we = cpu_wstrb;
muxed_rdata_new = ram_read_data; muxed_rdata_new = ram_read_data;
muxed_ready_new = ram_ready; muxed_ready_new = ram_ready;
end end
RESERVED_PREFIX: begin RESERVED_PREFIX: begin
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
MMIO_PREFIX: begin MMIO_PREFIX: begin
case (core_prefix) case (core_prefix)
TRNG_PREFIX: begin TRNG_PREFIX: begin
trng_cs = 1'h1; trng_cs = 1'h1;
muxed_rdata_new = trng_read_data; muxed_rdata_new = trng_read_data;
muxed_ready_new = trng_ready; muxed_ready_new = trng_ready;
end end
TIMER_PREFIX: begin TIMER_PREFIX: begin
timer_cs = 1'h1; timer_cs = 1'h1;
muxed_rdata_new = timer_read_data; muxed_rdata_new = timer_read_data;
muxed_ready_new = timer_ready; muxed_ready_new = timer_ready;
end end
UDS_PREFIX: begin UDS_PREFIX: begin
uds_cs = 1'h1; uds_cs = 1'h1;
muxed_rdata_new = uds_read_data; muxed_rdata_new = uds_read_data;
muxed_ready_new = uds_ready; muxed_ready_new = uds_ready;
end end
UART_PREFIX: begin UART_PREFIX: begin
uart_cs = 1'h1; uart_cs = 1'h1;
muxed_rdata_new = uart_read_data; muxed_rdata_new = uart_read_data;
muxed_ready_new = uart_ready; muxed_ready_new = uart_ready;
end end
TOUCH_SENSE_PREFIX: begin TOUCH_SENSE_PREFIX: begin
touch_sense_cs = 1'h1; touch_sense_cs = 1'h1;
muxed_rdata_new = touch_sense_read_data; muxed_rdata_new = touch_sense_read_data;
muxed_ready_new = touch_sense_ready; muxed_ready_new = touch_sense_ready;
end end
FW_RAM_PREFIX: begin FW_RAM_PREFIX: begin
fw_ram_cs = 1'h1; fw_ram_cs = 1'h1;
muxed_rdata_new = fw_ram_read_data; muxed_rdata_new = fw_ram_read_data;
muxed_ready_new = fw_ram_ready; muxed_ready_new = fw_ram_ready;
end end
TK1_PREFIX: begin TK1_PREFIX: begin
tk1_cs = 1'h1; tk1_cs = 1'h1;
muxed_rdata_new = tk1_read_data; muxed_rdata_new = tk1_read_data;
muxed_ready_new = tk1_ready; muxed_ready_new = tk1_ready;
end end
default: begin default: begin
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
endcase // case (core_prefix) endcase // case (core_prefix)
end // case: MMIO_PREFIX end // case: MMIO_PREFIX
default: begin default: begin
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
endcase // case (area_prefix) endcase // case (area_prefix)
end
end end
end end
end
endmodule // application_fpga endmodule // application_fpga
//====================================================================== //======================================================================
// EOF application_fpga.v // EOF application_fpga.v

562
hw/application_fpga/tb/application_fpga_vsim.v
View File

@ -18,64 +18,64 @@
//`define VERBOSE //`define VERBOSE
`ifdef VERBOSE `ifdef VERBOSE
`define verbose(debug_command) debug_command `define verbose(debug_command) debug_command
`else `else
`define verbose(debug_command) `define verbose(debug_command)
`endif `endif
module application_fpga( module application_fpga (
input wire clk, input wire clk,
output wire valid, output wire valid,
output wire [03 : 0] wstrb, output wire [03 : 0] wstrb,
output wire [31 : 0] addr, output wire [31 : 0] addr,
output wire [31 : 0] wdata, output wire [31 : 0] wdata,
output wire [31 : 0] rdata, output wire [31 : 0] rdata,
output wire ready, output wire ready,
output wire interface_rx, output wire interface_rx,
input wire interface_tx, input wire interface_tx,
input wire touch_event, input wire touch_event,
input wire app_gpio1, input wire app_gpio1,
input wire app_gpio2, input wire app_gpio2,
output wire app_gpio3, output wire app_gpio3,
output wire app_gpio4, output wire app_gpio4,
output wire led_r, output wire led_r,
output wire led_g, output wire led_g,
output wire led_b output wire led_b
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Local parameters // Local parameters
//---------------------------------------------------------------- //----------------------------------------------------------------
// Top level mem area prefixes. // Top level mem area prefixes.
localparam ROM_PREFIX = 2'h0; localparam ROM_PREFIX = 2'h0;
localparam RAM_PREFIX = 2'h1; localparam RAM_PREFIX = 2'h1;
localparam RESERVED_PREFIX = 2'h2; localparam RESERVED_PREFIX = 2'h2;
localparam MMIO_PREFIX = 2'h3; localparam MMIO_PREFIX = 2'h3;
// MMIO core mem sub-prefixes. // MMIO core mem sub-prefixes.
localparam TRNG_PREFIX = 6'h00; localparam TRNG_PREFIX = 6'h00;
localparam TIMER_PREFIX = 6'h01; localparam TIMER_PREFIX = 6'h01;
localparam UDS_PREFIX = 6'h02; localparam UDS_PREFIX = 6'h02;
localparam UART_PREFIX = 6'h03; localparam UART_PREFIX = 6'h03;
localparam TOUCH_SENSE_PREFIX = 6'h04; localparam TOUCH_SENSE_PREFIX = 6'h04;
localparam TK1_PREFIX = 6'h3f; localparam TK1_PREFIX = 6'h3f;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers, memories with associated wires. // Registers, memories with associated wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] muxed_rdata_reg; reg [31 : 0] muxed_rdata_reg;
reg [31 : 0] muxed_rdata_new; reg [31 : 0] muxed_rdata_new;
reg muxed_ready_reg; reg muxed_ready_reg;
reg muxed_ready_new; reg muxed_ready_new;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -96,7 +96,7 @@ module application_fpga(
wire rom_ready; wire rom_ready;
reg ram_cs; reg ram_cs;
reg [3 : 0] ram_we; reg [ 3 : 0] ram_we;
reg [14 : 0] ram_address; reg [14 : 0] ram_address;
reg [31 : 0] ram_write_data; reg [31 : 0] ram_write_data;
wire [31 : 0] ram_read_data; wire [31 : 0] ram_read_data;
@ -106,8 +106,8 @@ module application_fpga(
reg trng_cs; reg trng_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg trng_we; reg trng_we;
reg [7 : 0] trng_address; reg [ 7 : 0] trng_address;
reg [31 : 0] trng_write_data; reg [31 : 0] trng_write_data;
wire [31 : 0] trng_read_data; wire [31 : 0] trng_read_data;
wire trng_ready; wire trng_ready;
@ -115,7 +115,7 @@ module application_fpga(
reg timer_cs; reg timer_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg timer_we; reg timer_we;
reg [7 : 0] timer_address; reg [ 7 : 0] timer_address;
reg [31 : 0] timer_write_data; reg [31 : 0] timer_write_data;
wire [31 : 0] timer_read_data; wire [31 : 0] timer_read_data;
wire timer_ready; wire timer_ready;
@ -123,7 +123,7 @@ module application_fpga(
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
reg uds_cs; reg uds_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg [7 : 0] uds_address; reg [ 7 : 0] uds_address;
wire [31 : 0] uds_read_data; wire [31 : 0] uds_read_data;
wire uds_ready; wire uds_ready;
@ -131,7 +131,7 @@ module application_fpga(
reg uart_cs; reg uart_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg uart_we; reg uart_we;
reg [7 : 0] uart_address; reg [ 7 : 0] uart_address;
reg [31 : 0] uart_write_data; reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data; wire [31 : 0] uart_read_data;
wire uart_ready; wire uart_ready;
@ -140,7 +140,7 @@ module application_fpga(
reg touch_sense_cs; reg touch_sense_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg touch_sense_we; reg touch_sense_we;
reg [7 : 0] touch_sense_address; reg [ 7 : 0] touch_sense_address;
wire [31 : 0] touch_sense_read_data; wire [31 : 0] touch_sense_read_data;
wire touch_sense_ready; wire touch_sense_ready;
@ -148,8 +148,8 @@ module application_fpga(
reg tk1_cs; reg tk1_cs;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
reg tk1_we; reg tk1_we;
reg [7 : 0] tk1_address; reg [ 7 : 0] tk1_address;
reg [31 : 0] tk1_write_data; reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire fw_app_mode; wire fw_app_mode;
@ -169,310 +169,312 @@ module application_fpga(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Module instantiations. // Module instantiations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reset_gen #(.RESET_CYCLES(200)) reset_gen #(
reset_gen_inst(.clk(clk), .rst_n(reset_n)); .RESET_CYCLES(200)
) reset_gen_inst (
.clk (clk),
.rst_n(reset_n)
);
picorv32 #( picorv32 #(
.ENABLE_COUNTERS(0), .ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(0), .LATCHED_MEM_RDATA(0),
.TWO_STAGE_SHIFT(0), .TWO_STAGE_SHIFT(0),
.TWO_CYCLE_ALU(0), .TWO_CYCLE_ALU(0),
.CATCH_MISALIGN(0), .CATCH_MISALIGN(0),
.CATCH_ILLINSN(0), .CATCH_ILLINSN(0),
.COMPRESSED_ISA(1), .COMPRESSED_ISA(1),
.ENABLE_MUL(1), .ENABLE_MUL(1),
.ENABLE_DIV(0), .ENABLE_DIV(0),
.BARREL_SHIFTER(0) .BARREL_SHIFTER(0)
) cpu( ) cpu (
.clk(clk), .clk(clk),
.resetn(reset_n), .resetn(reset_n),
.mem_valid(cpu_valid), .mem_valid(cpu_valid),
.mem_addr (cpu_addr), .mem_addr (cpu_addr),
.mem_wdata(cpu_wdata), .mem_wdata(cpu_wdata),
.mem_wstrb(cpu_wstrb), .mem_wstrb(cpu_wstrb),
.mem_rdata(muxed_rdata_reg), .mem_rdata(muxed_rdata_reg),
.mem_ready(muxed_ready_reg), .mem_ready(muxed_ready_reg),
// Defined unsed ports. Makes lint happy, // Defined unsed ports. Makes lint happy,
// but still needs to help lint with empty ports. // but still needs to help lint with empty ports.
/* verilator lint_off PINCONNECTEMPTY */ /* verilator lint_off PINCONNECTEMPTY */
.irq(32'h0), .irq(32'h0),
.eoi(), .eoi(),
.trap(), .trap(),
.trace_valid(), .trace_valid(),
.trace_data(), .trace_data(),
.mem_instr(), .mem_instr(),
.mem_la_read(), .mem_la_read(),
.mem_la_write(), .mem_la_write(),
.mem_la_addr(), .mem_la_addr(),
.mem_la_wdata(), .mem_la_wdata(),
.mem_la_wstrb(), .mem_la_wstrb(),
.pcpi_valid(), .pcpi_valid(),
.pcpi_insn(), .pcpi_insn(),
.pcpi_rs1(), .pcpi_rs1(),
.pcpi_rs2(), .pcpi_rs2(),
.pcpi_wr(1'h0), .pcpi_wr(1'h0),
.pcpi_rd(32'h0), .pcpi_rd(32'h0),
.pcpi_wait(1'h0), .pcpi_wait(1'h0),
.pcpi_ready(1'h0) .pcpi_ready(1'h0)
/* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_on PINCONNECTEMPTY */
); );
rom rom_inst( rom rom_inst (
.cs(rom_cs), .cs(rom_cs),
.address(rom_address), .address(rom_address),
.read_data(rom_read_data), .read_data(rom_read_data),
.ready(rom_ready) .ready(rom_ready)
); );
ram ram_inst( ram ram_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cs(ram_cs), .cs(ram_cs),
.we(ram_we), .we(ram_we),
.address(ram_address), .address(ram_address),
.write_data(ram_write_data), .write_data(ram_write_data),
.read_data(ram_read_data), .read_data(ram_read_data),
.ready(ram_ready) .ready(ram_ready)
); );
timer timer_inst( timer timer_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cs(timer_cs), .cs(timer_cs),
.we(timer_we), .we(timer_we),
.address(timer_address), .address(timer_address),
.write_data(timer_write_data), .write_data(timer_write_data),
.read_data(timer_read_data), .read_data(timer_read_data),
.ready(timer_ready) .ready(timer_ready)
); );
uds uds_inst( uds uds_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.cs(uds_cs), .cs(uds_cs),
.address(uds_address), .address(uds_address),
.read_data(uds_read_data), .read_data(uds_read_data),
.ready(uds_ready) .ready(uds_ready)
); );
uart uart_inst( uart uart_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.rxd(interface_tx), .rxd(interface_tx),
.txd(interface_rx), .txd(interface_rx),
.cs(uart_cs), .cs(uart_cs),
.we(uart_we), .we(uart_we),
.address(uart_address), .address(uart_address),
.write_data(uart_write_data), .write_data(uart_write_data),
.read_data(uart_read_data), .read_data(uart_read_data),
.ready(uart_ready) .ready(uart_ready)
); );
touch_sense touch_sense_inst( touch_sense touch_sense_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.touch_event(touch_event), .touch_event(touch_event),
.cs(touch_sense_cs), .cs(touch_sense_cs),
.we(touch_sense_we), .we(touch_sense_we),
.address(touch_sense_address), .address(touch_sense_address),
.read_data(touch_sense_read_data), .read_data(touch_sense_read_data),
.ready(touch_sense_ready) .ready(touch_sense_ready)
); );
tk1 tk1_inst( tk1 tk1_inst (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .fw_app_mode(fw_app_mode),
.led_r(led_r), .led_r(led_r),
.led_g(led_g), .led_g(led_g),
.led_b(led_b), .led_b(led_b),
.gpio1(app_gpio1), .gpio1(app_gpio1),
.gpio2(app_gpio2), .gpio2(app_gpio2),
.gpio3(app_gpio3), .gpio3(app_gpio3),
.gpio4(app_gpio4), .gpio4(app_gpio4),
.cs(tk1_cs), .cs(tk1_cs),
.we(tk1_we), .we(tk1_we),
.address(tk1_address), .address(tk1_address),
.write_data(tk1_write_data), .write_data(tk1_write_data),
.read_data(tk1_read_data), .read_data(tk1_read_data),
.ready(tk1_ready) .ready(tk1_ready)
); );
//---------------------------------------------------------------- //----------------------------------------------------------------
// Reg_update. // Reg_update.
// Posedge triggered with synchronous, active low reset. // Posedge triggered with synchronous, active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update if (!reset_n) begin
if (!reset_n) begin muxed_ready_reg <= 1'h0;
muxed_ready_reg <= 1'h0; muxed_rdata_reg <= 32'h0;
muxed_rdata_reg <= 32'h0;
end
else begin
muxed_ready_reg <= muxed_ready_new;
muxed_rdata_reg <= muxed_rdata_new;
end
end end
else begin
muxed_ready_reg <= muxed_ready_new;
muxed_rdata_reg <= muxed_rdata_new;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// cpu_mem_ctrl // cpu_mem_ctrl
// CPU memory decode and control logic. // CPU memory decode and control logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : cpu_mem_ctrl
begin : cpu_mem_ctrl reg [1 : 0] area_prefix;
reg [1 : 0] area_prefix; reg [5 : 0] core_prefix;
reg [5 : 0] core_prefix;
area_prefix = cpu_addr[31 : 30]; area_prefix = cpu_addr[31 : 30];
core_prefix = cpu_addr[29 : 24]; core_prefix = cpu_addr[29 : 24];
muxed_ready_new = 1'h0; muxed_ready_new = 1'h0;
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
rom_cs = 1'h0; rom_cs = 1'h0;
rom_address = cpu_addr[13 : 2]; rom_address = cpu_addr[13 : 2];
ram_cs = 1'h0; ram_cs = 1'h0;
ram_we = cpu_wstrb; ram_we = cpu_wstrb;
ram_address = cpu_addr[16 : 2]; ram_address = cpu_addr[16 : 2];
ram_write_data = cpu_wdata; ram_write_data = cpu_wdata;
trng_cs = 1'h0; trng_cs = 1'h0;
trng_we = |cpu_wstrb; trng_we = |cpu_wstrb;
trng_address = cpu_addr[9 : 2]; trng_address = cpu_addr[9 : 2];
trng_write_data = cpu_wdata; trng_write_data = cpu_wdata;
timer_cs = 1'h0; timer_cs = 1'h0;
timer_we = |cpu_wstrb; timer_we = |cpu_wstrb;
timer_address = cpu_addr[9 : 2]; timer_address = cpu_addr[9 : 2];
timer_write_data = cpu_wdata; timer_write_data = cpu_wdata;
uds_cs = 1'h0; uds_cs = 1'h0;
uds_address = cpu_addr[9 : 2]; uds_address = cpu_addr[9 : 2];
uart_cs = 1'h0; uart_cs = 1'h0;
uart_we = |cpu_wstrb; uart_we = |cpu_wstrb;
uart_address = cpu_addr[9 : 2]; uart_address = cpu_addr[9 : 2];
uart_write_data = cpu_wdata; uart_write_data = cpu_wdata;
touch_sense_cs = 1'h0; touch_sense_cs = 1'h0;
touch_sense_we = |cpu_wstrb; touch_sense_we = |cpu_wstrb;
touch_sense_address = cpu_addr[9 : 2]; touch_sense_address = cpu_addr[9 : 2];
tk1_cs = 1'h0; tk1_cs = 1'h0;
tk1_we = |cpu_wstrb; tk1_we = |cpu_wstrb;
tk1_address = cpu_addr[9 : 2]; tk1_address = cpu_addr[9 : 2];
tk1_write_data = cpu_wdata; tk1_write_data = cpu_wdata;
if (cpu_valid && !muxed_ready_reg) begin if (cpu_valid && !muxed_ready_reg) begin
case (area_prefix) case (area_prefix)
ROM_PREFIX: begin ROM_PREFIX: begin
`verbose($display("Access to ROM area");) `verbose($display("Access to ROM area");)
rom_cs = 1'h1; rom_cs = 1'h1;
muxed_rdata_new = rom_read_data; muxed_rdata_new = rom_read_data;
muxed_ready_new = rom_ready; muxed_ready_new = rom_ready;
end end
RAM_PREFIX: begin RAM_PREFIX: begin
`verbose($display("Access to RAM area");) `verbose($display("Access to RAM area");)
ram_cs = 1'h1; ram_cs = 1'h1;
muxed_rdata_new = ram_read_data; muxed_rdata_new = ram_read_data;
muxed_ready_new = ram_ready; muxed_ready_new = ram_ready;
end end
RESERVED_PREFIX: begin RESERVED_PREFIX: begin
`verbose($display("Access to RESERVED area");) `verbose($display("Access to RESERVED area");)
muxed_rdata_new = 32'h00000000; muxed_rdata_new = 32'h00000000;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
MMIO_PREFIX: begin MMIO_PREFIX: begin
`verbose($display("Access to MMIO area");) `verbose($display("Access to MMIO area");)
case (core_prefix) case (core_prefix)
TRNG_PREFIX: begin TRNG_PREFIX: begin
`verbose($display("Access to TRNG core");) `verbose($display("Access to TRNG core");)
trng_cs = 1'h1; trng_cs = 1'h1;
muxed_rdata_new = trng_read_data; muxed_rdata_new = trng_read_data;
muxed_ready_new = trng_ready; muxed_ready_new = trng_ready;
end end
TIMER_PREFIX: begin TIMER_PREFIX: begin
`verbose($display("Access to TIMER core");) `verbose($display("Access to TIMER core");)
timer_cs = 1'h1; timer_cs = 1'h1;
muxed_rdata_new = timer_read_data; muxed_rdata_new = timer_read_data;
muxed_ready_new = timer_ready; muxed_ready_new = timer_ready;
end end
UDS_PREFIX: begin UDS_PREFIX: begin
`verbose($display("Access to UDS core");) `verbose($display("Access to UDS core");)
uds_cs = 1'h1; uds_cs = 1'h1;
muxed_rdata_new = uds_read_data; muxed_rdata_new = uds_read_data;
muxed_ready_new = uds_ready; muxed_ready_new = uds_ready;
end end
UART_PREFIX: begin UART_PREFIX: begin
`verbose($display("Access to UART core");) `verbose($display("Access to UART core");)
uart_cs = 1'h1; uart_cs = 1'h1;
muxed_rdata_new = uart_read_data; muxed_rdata_new = uart_read_data;
muxed_ready_new = uart_ready; muxed_ready_new = uart_ready;
end end
TOUCH_SENSE_PREFIX: begin TOUCH_SENSE_PREFIX: begin
`verbose($display("Access to TOUCH_SENSE core");) `verbose($display("Access to TOUCH_SENSE core");)
touch_sense_cs = 1'h1; touch_sense_cs = 1'h1;
muxed_rdata_new = touch_sense_read_data; muxed_rdata_new = touch_sense_read_data;
muxed_ready_new = touch_sense_ready; muxed_ready_new = touch_sense_ready;
end end
TK1_PREFIX: begin TK1_PREFIX: begin
`verbose($display("Access to TK1 core");) `verbose($display("Access to TK1 core");)
tk1_cs = 1'h1; tk1_cs = 1'h1;
muxed_rdata_new = tk1_read_data; muxed_rdata_new = tk1_read_data;
muxed_ready_new = tk1_ready; muxed_ready_new = tk1_ready;
end end
default: begin default: begin
`verbose($display("UNDEFINED MMIO");) `verbose($display("UNDEFINED MMIO");)
muxed_rdata_new = 32'h00000000; muxed_rdata_new = 32'h00000000;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
endcase // case (core_prefix) endcase // case (core_prefix)
end // case: MMIO_PREFIX end // case: MMIO_PREFIX
default: begin default: begin
`verbose($display("UNDEFINED AREA");) `verbose($display("UNDEFINED AREA");)
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
endcase // case (area_prefix) endcase // case (area_prefix)
end
end end
end
endmodule // application_fpga endmodule // application_fpga
//====================================================================== //======================================================================
// EOF application_fpga.v // EOF application_fpga.v

42
hw/application_fpga/tb/reset_gen_vsim.v
View File

@ -13,11 +13,12 @@
`default_nettype none `default_nettype none
module reset_gen #(parameter RESET_CYCLES = 200) module reset_gen #(
( parameter RESET_CYCLES = 200
input wire clk, ) (
output wire rst_n input wire clk,
); output wire rst_n
);
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -40,32 +41,29 @@ module reset_gen #(parameter RESET_CYCLES = 200)
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update. // reg_update.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update rst_n_reg <= rst_n_new;
rst_n_reg <= rst_n_new;
if (rst_ctr_we) if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
rst_ctr_reg <= rst_ctr_new; end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// rst_logic. // rst_logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rst_logic
begin : rst_logic rst_n_new = 1'h1;
rst_n_new = 1'h1; rst_ctr_new = 8'h0;
rst_ctr_new = 8'h0; rst_ctr_we = 1'h0;
rst_ctr_we = 1'h0;
if (rst_ctr_reg < RESET_CYCLES) begin if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0; rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1; rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1; rst_ctr_we = 1'h1;
end
end end
end
endmodule // reset_gen endmodule // reset_gen
//====================================================================== //======================================================================
// EOF reset_gen.v // EOF reset_gen.v