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FPGA: Format verilog code

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This commit is contained in:
Jonas Thörnblad 2024-10-22 11:54:56 +02:00 • committed by Daniel Jobson
parent e04aacda48
commit 3514d7ef3c
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GPG key ID: 3707A9DBF4BB8F1A
30 changed files with 3477 additions and 3579 deletions
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23
hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
View file

@ -16,8 +16,9 @@
`default_nettype none `default_nettype none
module clk_reset_gen #(parameter RESET_CYCLES = 200) module clk_reset_gen #(
( parameter RESET_CYCLES = 200
) (
input wire sys_reset, input wire sys_reset,
output wire clk, output wire clk,
@ -58,8 +59,13 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
// Use the FPGA internal High Frequency OSCillator as clock source. // Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
SB_HFOSC #(.CLKHF_DIV("0b10") SB_HFOSC #(
) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk)); .CLKHF_DIV("0b10")
) hfosc_inst (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (hfosc_clk)
);
// Use a PLL to generate a new clock frequency based on the HFOSC clock. // Use a PLL to generate a new clock frequency based on the HFOSC clock.
@ -99,21 +105,18 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update. // reg_update.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
rst_n_reg <= rst_n_new; rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset; sys_reset_reg <= sys_reset;
if (rst_ctr_we) if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
rst_ctr_reg <= rst_ctr_new;
end end
//---------------------------------------------------------------- //----------------------------------------------------------------
// rst_logic. // rst_logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rst_logic
begin : rst_logic
rst_n_new = 1'h1; rst_n_new = 1'h1;
rst_ctr_new = 8'h0; rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0; rst_ctr_we = 1'h0;

6
hw/application_fpga/core/fw_ram/rtl/fw_ram.v
View file

@ -111,8 +111,7 @@ module fw_ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
ready_reg <= 1'h0; ready_reg <= 1'h0;
end end
@ -125,8 +124,7 @@ module fw_ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
// rw_mux // rw_mux
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rw_mux
begin : rw_mux;
bank0 = 1'h0; bank0 = 1'h0;
bank1 = 1'h0; bank1 = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;

14
hw/application_fpga/core/ram/rtl/ram.v
View file

@ -26,7 +26,7 @@ module ram(
input wire [31 : 0] ram_data_rand, input wire [31 : 0] ram_data_rand,
input wire cs, input wire cs,
input wire [03 : 0] we, input wire [ 3 : 0] we,
input wire [15 : 0] address, input wire [15 : 0] address,
input wire [31 : 0] write_data, input wire [31 : 0] write_data,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
@ -121,8 +121,7 @@ module ram(
// This simply creates a one cycle access latency to match // This simply creates a one cycle access latency to match
// the latency of the spram blocks. // the latency of the spram blocks.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
ready_reg <= 1'h0; ready_reg <= 1'h0;
end end
@ -138,8 +137,7 @@ module ram(
// Scramble address and write data, and descramble read data using // Scramble address and write data, and descramble read data using
// the ram_addr_rand and ram_data_rand seeds. // the ram_addr_rand and ram_data_rand seeds.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : scramble_descramble
begin: scramble_descramble
scrambled_ram_addr = address[14 : 0] ^ ram_addr_rand; scrambled_ram_addr = address[14 : 0] ^ ram_addr_rand;
scrambled_write_data = write_data ^ ram_data_rand ^ {2{address}}; scrambled_write_data = write_data ^ ram_data_rand ^ {2{address}};
descrambled_read_data = muxed_read_data ^ ram_data_rand ^ {2{address}}; descrambled_read_data = muxed_read_data ^ ram_data_rand ^ {2{address}};
@ -152,14 +150,14 @@ module ram(
// Select which of the data read from the banks should be // Select which of the data read from the banks should be
// returned during a read access. // returned during a read access.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : mem_mux
begin : mem_mux
cs0 = ~scrambled_ram_addr[14] & cs; cs0 = ~scrambled_ram_addr[14] & cs;
cs1 = scrambled_ram_addr[14] & cs; cs1 = scrambled_ram_addr[14] & cs;
if (scrambled_ram_addr[14]) begin if (scrambled_ram_addr[14]) begin
muxed_read_data = read_data1; muxed_read_data = read_data1;
end else begin end
else begin
muxed_read_data = read_data0; muxed_read_data = read_data0;
end end
end end

6
hw/application_fpga/core/rom/rtl/rom.v
View file

@ -58,8 +58,7 @@ module rom(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
ready_reg <= 1'h0; ready_reg <= 1'h0;
end end
@ -72,8 +71,7 @@ module rom(
//---------------------------------------------------------------- //----------------------------------------------------------------
// rom_logic // rom_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rom_logic
begin : rom_logic
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
rom_rdata = memory[address]; rom_rdata = memory[address];
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */

6
hw/application_fpga/core/timer/rtl/timer.v
View file

@ -94,8 +94,7 @@ module timer(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
start_reg <= 1'h0; start_reg <= 1'h0;
stop_reg <= 1'h0; stop_reg <= 1'h0;
@ -122,8 +121,7 @@ module timer(
// //
// The interface command decoding logic. // The interface command decoding logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api
start_new = 1'h0; start_new = 1'h0;
stop_new = 1'h0; stop_new = 1'h0;
prescaler_we = 1'h0; prescaler_we = 1'h0;

18
hw/application_fpga/core/timer/rtl/timer_core.v
View file

@ -69,17 +69,14 @@ module timer_core(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update if (!reset_n) begin
if (!reset_n)
begin
running_reg <= 1'h0; running_reg <= 1'h0;
prescaler_reg <= 32'h0; prescaler_reg <= 32'h0;
timer_reg <= 32'h0; timer_reg <= 32'h0;
core_ctrl_reg <= CTRL_IDLE; core_ctrl_reg <= CTRL_IDLE;
end end
else else begin
begin
if (running_we) begin if (running_we) begin
running_reg <= running_new; running_reg <= running_new;
end end
@ -102,8 +99,7 @@ module timer_core(
//---------------------------------------------------------------- //----------------------------------------------------------------
// prescaler_ctr // prescaler_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : prescaler_ctr
begin : prescaler_ctr
prescaler_new = 32'h0; prescaler_new = 32'h0;
prescaler_we = 1'h0; prescaler_we = 1'h0;
@ -121,8 +117,7 @@ module timer_core(
//---------------------------------------------------------------- //----------------------------------------------------------------
// timer_ctr // timer_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : timer_ctr
begin : timer_ctr
timer_new = 32'h0; timer_new = 32'h0;
timer_we = 1'h0; timer_we = 1'h0;
@ -140,8 +135,7 @@ module timer_core(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Core control FSM. // Core control FSM.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : core_ctrl
begin : core_ctrl
running_new = 1'h0; running_new = 1'h0;
running_we = 1'h0; running_we = 1'h0;
prescaler_set = 1'h0; prescaler_set = 1'h0;

36
hw/application_fpga/core/timer/tb/tb_timer.v
View file

@ -77,8 +77,7 @@ module tb_timer();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -90,12 +89,10 @@ module tb_timer();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (tb_monitor) if (tb_monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -113,13 +110,15 @@ module tb_timer();
$display("Cycle: %08d", cycle_ctr); $display("Cycle: %08d", cycle_ctr);
$display(""); $display("");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("cs: 0x%1x, we: 0x%1x, address: 0x%02x, write_data: 0x%08x, read_data: 0x%08x, ready: 0x%1x", $display(
"cs: 0x%1x, we: 0x%1x, address: 0x%02x, write_data: 0x%08x, read_data: 0x%08x, ready: 0x%1x",
tb_cs, tb_we, tb_address, tb_write_data, tb_read_data, tb_ready); tb_cs, tb_we, tb_address, tb_write_data, tb_read_data, tb_ready);
$display(""); $display("");
$display("Internal state:"); $display("Internal state:");
$display("prescaler_reg: 0x%08x, timer_reg: 0x%08x", dut.prescaler_reg, dut.timer_reg); $display("prescaler_reg: 0x%08x, timer_reg: 0x%08x", dut.prescaler_reg, dut.timer_reg);
$display("start_reg: 0x%1x, stop_reg: 0x%1x", dut.start_reg, dut.stop_reg); $display("start_reg: 0x%1x, stop_reg: 0x%1x", dut.start_reg, dut.stop_reg);
$display("core_running: 0x%1x, core_curr_timer: 0x%08x", dut.core_running, dut.core_curr_timer); $display("core_running: 0x%1x, core_curr_timer: 0x%08x", dut.core_running,
dut.core_curr_timer);
$display(""); $display("");
$display(""); $display("");
end end
@ -148,12 +147,10 @@ module tb_timer();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("--- All %02d test cases completed successfully", tc_ctr); $display("--- All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.", $display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr); tc_ctr, error_ctr);
end end
@ -189,11 +186,9 @@ module tb_timer();
// //
// Write the given word to the DUT using the DUT interface. // Write the given word to the DUT using the DUT interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
task write_word(input [11 : 0] address, task write_word(input [11 : 0] address, input [31 : 0] word);
input [31 : 0] word);
begin
if (DEBUG)
begin begin
if (DEBUG) begin
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("--- Writing 0x%08x to 0x%02x.", word, address);
$display(""); $display("");
end end
@ -225,8 +220,7 @@ module tb_timer();
read_data = tb_read_data; read_data = tb_read_data;
tb_cs = 0; tb_cs = 0;
if (DEBUG) if (DEBUG) begin
begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display(""); $display("");
end end
@ -242,8 +236,7 @@ module tb_timer();
task wait_ready; task wait_ready;
begin : wready begin : wready
read_word(ADDR_STATUS); read_word(ADDR_STATUS);
while (read_data == 0) while (read_data == 0) read_word(ADDR_STATUS);
read_word(ADDR_STATUS);
end end
endtask // wait_ready endtask // wait_ready
@ -292,8 +285,7 @@ module tb_timer();
//---------------------------------------------------------------- //----------------------------------------------------------------
// timer_test // timer_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : timer_test
begin : timer_test
$display(""); $display("");
$display(" -= Testbench for timer started =-"); $display(" -= Testbench for timer started =-");
$display(" ============================="); $display(" =============================");

37
hw/application_fpga/core/timer/tb/tb_timer_core.v
View file

@ -63,8 +63,7 @@ module tb_timer_core();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -76,12 +75,10 @@ module tb_timer_core();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (tb_monitor) if (tb_monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -99,21 +96,16 @@ module tb_timer_core();
$display("Cycle: %08d", cycle_ctr); $display("Cycle: %08d", cycle_ctr);
$display(""); $display("");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("prescaler_init: 0x%08x, timer_init: 0x%08x", $display("prescaler_init: 0x%08x, timer_init: 0x%08x", dut.prescaler_init, dut.timer_init);
dut.prescaler_init, dut.timer_init); $display("start: 0x%1x, stop: 0x%1x, running: 0x%1x", dut.start, dut.stop, dut.running);
$display("start: 0x%1x, stop: 0x%1x, running: 0x%1x",
dut.start, dut.stop, dut.running);
$display(""); $display("");
$display("Internal state:"); $display("Internal state:");
$display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x", $display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x", dut.prescaler_reg,
dut.prescaler_reg, dut.prescaler_new); dut.prescaler_new);
$display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x", $display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x", dut.prescaler_set, dut.prescaler_dec);
dut.prescaler_set, dut.prescaler_dec);
$display(""); $display("");
$display("timer_reg: 0x%08x, timer_new: 0x%08x", $display("timer_reg: 0x%08x, timer_new: 0x%08x", dut.timer_reg, dut.timer_new);
dut.timer_reg, dut.timer_new); $display("timer_set: 0x%1x, timer_dec: 0x%1x", dut.timer_set, dut.timer_dec);
$display("timer_set: 0x%1x, timer_dec: 0x%1x",
dut.timer_set, dut.timer_dec);
$display(""); $display("");
$display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x", $display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x",
dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we); dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
@ -154,11 +146,9 @@ module tb_timer_core();
task wait_done; task wait_done;
begin begin
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
while (tb_running) while (tb_running) begin
begin
#(CLK_PERIOD); #(CLK_PERIOD);
if (DUMP_WAIT) if (DUMP_WAIT) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -220,8 +210,7 @@ module tb_timer_core();
// //
// Test vectors from: // Test vectors from:
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : timer_core_test
begin : timer_core_test
$display("--- Simulation of timer core started."); $display("--- Simulation of timer core started.");
$display(""); $display("");

24
hw/application_fpga/core/tk1/rtl/tk1.v
View file

@ -246,8 +246,7 @@ module tk1(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
switch_app_reg <= 1'h0; switch_app_reg <= 1'h0;
led_reg <= 3'h6; led_reg <= 3'h6;
@ -354,8 +353,7 @@ module tk1(
//---------------------------------------------------------------- //----------------------------------------------------------------
// trap_led_logic // trap_led_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : trap_led_logic
begin : trap_led_logic
cpu_trap_led_new = 3'h0; cpu_trap_led_new = 3'h0;
cpu_trap_led_we = 1'h0; cpu_trap_led_we = 1'h0;
@ -368,7 +366,8 @@ module tk1(
if (cpu_trap) begin if (cpu_trap) begin
muxed_led = cpu_trap_led_reg; muxed_led = cpu_trap_led_reg;
end else begin end
else begin
muxed_led = led_reg; muxed_led = led_reg;
end end
end end
@ -388,8 +387,7 @@ module tk1(
// This requires execution monitor to have been setup and // This requires execution monitor to have been setup and
// enabled. // enabled.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : security_monitor
begin : security_monitor
force_trap_set = 1'h0; force_trap_set = 1'h0;
if (cpu_valid) begin if (cpu_valid) begin
@ -398,14 +396,12 @@ module tk1(
end end
if (cpu_instr) begin if (cpu_instr) begin
if ((cpu_addr >= FW_RAM_FIRST) && if ((cpu_addr >= FW_RAM_FIRST) && (cpu_addr <= FW_RAM_LAST)) begin
(cpu_addr <= FW_RAM_LAST)) begin
force_trap_set = 1'h1; force_trap_set = 1'h1;
end end
if (cpu_mon_en_reg) begin if (cpu_mon_en_reg) begin
if ((cpu_addr >= cpu_mon_first_reg) && if ((cpu_addr >= cpu_mon_first_reg) && (cpu_addr <= cpu_mon_last_reg)) begin
(cpu_addr <= cpu_mon_last_reg)) begin
force_trap_set = 1'h1; force_trap_set = 1'h1;
end end
end end
@ -417,8 +413,7 @@ module tk1(
//---------------------------------------------------------------- //----------------------------------------------------------------
// api // api
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api
switch_app_we = 1'h0; switch_app_we = 1'h0;
led_we = 1'h0; led_we = 1'h0;
gpio3_we = 1'h0; gpio3_we = 1'h0;
@ -552,8 +547,7 @@ module tk1(
end end
if (address == ADDR_GPIO) begin if (address == ADDR_GPIO) begin
tmp_read_data = {28'h0, gpio4_reg, gpio3_reg, tmp_read_data = {28'h0, gpio4_reg, gpio3_reg, gpio2_reg[1], gpio1_reg[1]};
gpio2_reg[1], gpio1_reg[1]};
end end
if (address == ADDR_APP_START) begin if (address == ADDR_APP_START) begin

15
hw/application_fpga/core/tk1/rtl/tk1_spi_master.v
View file

@ -100,8 +100,7 @@ module tk1_spi_master(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
spi_ss_reg <= 1'h1; spi_ss_reg <= 1'h1;
spi_csk_reg <= 1'h0; spi_csk_reg <= 1'h0;
@ -150,8 +149,7 @@ module tk1_spi_master(
//---------------------------------------------------------------- //----------------------------------------------------------------
// bit_ctr // bit_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : bit_ctr
begin : bit_ctr
spi_bit_ctr_new = 3'h0; spi_bit_ctr_new = 3'h0;
spi_bit_ctr_we = 1'h0; spi_bit_ctr_we = 1'h0;
@ -173,8 +171,7 @@ module tk1_spi_master(
// Logic for the tx_data shift register. // Logic for the tx_data shift register.
// Either load or shift the data register. // Either load or shift the data register.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : spi_tx_data_logic
begin : spi_tx_data_logic
spi_tx_data_new = 8'h0; spi_tx_data_new = 8'h0;
spi_tx_data_we = 1'h0; spi_tx_data_we = 1'h0;
@ -196,8 +193,7 @@ module tk1_spi_master(
// spi_rx_data_logic // spi_rx_data_logic
// Logic for the rx_data shift register. // Logic for the rx_data shift register.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : spi_rx_data_logic
begin : spi_rx_data_logic
spi_rx_data_new = 8'h0; spi_rx_data_new = 8'h0;
spi_rx_data_we = 1'h0; spi_rx_data_we = 1'h0;
@ -216,8 +212,7 @@ module tk1_spi_master(
//---------------------------------------------------------------- //----------------------------------------------------------------
// spi_master_ctrl // spi_master_ctrl
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : spi_master_ctrl
begin : spi_master_ctrl
spi_rx_data_nxt = 1'h0; spi_rx_data_nxt = 1'h0;
spi_tx_data_nxt = 1'h0; spi_tx_data_nxt = 1'h0;
spi_csk_new = 1'h0; spi_csk_new = 1'h0;

6
hw/application_fpga/core/tk1/rtl/udi_rom.v
View file

@ -19,10 +19,10 @@ module udi_rom (
generate generate
genvar ii; genvar ii;
/* verilator lint_off PINMISSING */ /* verilator lint_off PINMISSING */
for (ii = 0; ii < 32; ii = ii + 1'b1) for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts
begin: luts
(* udi_rom_idx=ii, keep *) SB_LUT4 #(.LUT_INIT({2'h1}) (* udi_rom_idx=ii, keep *) SB_LUT4 #(
.LUT_INIT({2'h1})
) lut_i ( ) lut_i (
.I0(addr[0]), .I0(addr[0]),
.O (data[ii]) .O (data[ii])

60
hw/application_fpga/core/tk1/tb/tb_tk1.v
View file

@ -160,8 +160,7 @@ module tb_tk1();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -173,12 +172,10 @@ module tb_tk1();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (tb_monitor) if (tb_monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -198,9 +195,11 @@ module tb_tk1();
$display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode); $display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode);
$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x", $display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap); tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand, tb_ram_data_rand); $display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand,
tb_ram_data_rand);
$display("led_r: 0x%1x, led_g: 0x%1x, led_b: 0x%1x", tb_led_r, tb_led_g, tb_led_b); $display("led_r: 0x%1x, led_g: 0x%1x, led_b: 0x%1x", tb_led_r, tb_led_g, tb_led_b);
$display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we, tb_address); $display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we,
tb_address);
$display("write_data: 0x%08x, read_data: 0x%08x", tb_write_data, tb_read_data); $display("write_data: 0x%08x, read_data: 0x%08x", tb_write_data, tb_read_data);
$display(""); $display("");
@ -211,8 +210,8 @@ module tb_tk1();
if (tb_spi_monitor) begin if (tb_spi_monitor) begin
$display("SPI I/O and internal state:"); $display("SPI I/O and internal state:");
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso: 0x%1x", $display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso: 0x%1x", tb_spi_ss,
tb_spi_ss, tb_spi_sck, tb_spi_mosi, tb_spi_miso); tb_spi_sck, tb_spi_mosi, tb_spi_miso);
end end
$display(""); $display("");
@ -243,12 +242,10 @@ module tb_tk1();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("--- All %02d test cases completed successfully", tc_ctr); $display("--- All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("--- %02d tests completed - %02d errors detected.", tc_ctr, error_ctr); $display("--- %02d tests completed - %02d errors detected.", tc_ctr, error_ctr);
end end
end end
@ -293,11 +290,9 @@ module tb_tk1();
// //
// Write the given word to the DUT using the DUT interface. // Write the given word to the DUT using the DUT interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
task write_word(input [11 : 0] address, task write_word(input [11 : 0] address, input [31 : 0] word);
input [31 : 0] word);
begin
if (DEBUG)
begin begin
if (DEBUG) begin
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("--- Writing 0x%08x to 0x%02x.", word, address);
$display(""); $display("");
end end
@ -359,13 +354,13 @@ module tb_tk1();
#(CLK_PERIOD); #(CLK_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
if (DEBUG) if (DEBUG) begin
begin
if (read_data == expected) begin if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin end
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", else begin
read_data, address, expected); $display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1; error_ctr = error_ctr + 1;
end end
$display(""); $display("");
@ -563,8 +558,10 @@ module tb_tk1();
write_word(ADDR_RAM_ADDR_RAND, 32'h13371337); write_word(ADDR_RAM_ADDR_RAND, 32'h13371337);
write_word(ADDR_RAM_DATA_RAND, 32'h47114711); write_word(ADDR_RAM_DATA_RAND, 32'h47114711);
$display("--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers."); $display(
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x", dut.ram_addr_rand, dut.ram_data_rand); "--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: Switch to app mode."); $display("--- test6: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hf000000); write_word(ADDR_SWITCH_APP, 32'hf000000);
@ -573,8 +570,10 @@ module tb_tk1();
write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef); write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef);
write_word(ADDR_RAM_DATA_RAND, 32'hf00ff00f); write_word(ADDR_RAM_DATA_RAND, 32'hf00ff00f);
$display("--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers."); $display(
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x", dut.ram_addr_rand, dut.ram_data_rand); "--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: completed."); $display("--- test6: completed.");
$display(""); $display("");
@ -664,8 +663,8 @@ module tb_tk1();
tb_cpu_instr = 1'h1; tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1; tb_cpu_valid = 1'h1;
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
$display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x", $display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x", tb_cpu_addr,
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid); tb_cpu_instr, tb_cpu_valid);
$display("--- test9: force_trap: 0x%1x", tb_force_trap); $display("--- test9: force_trap: 0x%1x", tb_force_trap);
$display("--- test9: completed."); $display("--- test9: completed.");
@ -719,8 +718,7 @@ module tb_tk1();
//---------------------------------------------------------------- //----------------------------------------------------------------
// tk1_test // tk1_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : tk1_test
begin : tk1_test
$display(""); $display("");
$display(" -= Testbench for tk1 started =-"); $display(" -= Testbench for tk1 started =-");
$display(" ==========================="); $display(" ===========================");

86
hw/application_fpga/core/tk1/tb/tb_tk1_spi_master.v
View file

@ -11,8 +11,7 @@
// //
//====================================================================== //======================================================================
`default_nettype none `default_nettype none `timescale 1ns / 1ns
`timescale 1ns / 1ns
module tb_tk1_spi_master (); module tb_tk1_spi_master ();
@ -107,8 +106,7 @@ module tb_tk1_spi_master();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -120,12 +118,10 @@ module tb_tk1_spi_master();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (monitor) if (monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -142,14 +138,12 @@ module tb_tk1_spi_master();
$display("State of DUT at cycle: %08d", cycle_ctr); $display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------"); $display("------------");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x", $display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x", dut.spi_ss,
dut.spi_ss, dut.spi_sck, dut.spi_mosi, dut.spi_miso); dut.spi_sck, dut.spi_mosi, dut.spi_miso);
$display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x", $display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x", dut.spi_enable_vld, dut.spi_enable);
dut.spi_enable_vld, dut.spi_enable); $display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x", dut.spi_tx_data_vld, dut.spi_tx_data);
$display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x", $display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x", dut.spi_start,
dut.spi_tx_data_vld, dut.spi_tx_data); dut.spi_ready, dut.spi_rx_data);
$display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x",
dut.spi_start, dut.spi_ready, dut.spi_rx_data);
$display(""); $display("");
@ -158,35 +152,35 @@ module tb_tk1_spi_master();
$display("spi_bit_ctr_rst: 0x%1x, spi_bit_ctr_inc: 0x%1x, spi_bit_ctr_reg: 0x%02x", $display("spi_bit_ctr_rst: 0x%1x, spi_bit_ctr_inc: 0x%1x, spi_bit_ctr_reg: 0x%02x",
dut.spi_bit_ctr_rst, dut.spi_bit_ctr_inc, dut.spi_bit_ctr_reg); dut.spi_bit_ctr_rst, dut.spi_bit_ctr_inc, dut.spi_bit_ctr_reg);
$display(""); $display("");
$display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x", $display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x", dut.spi_ctrl_reg,
dut.spi_ctrl_reg, dut.spi_ctrl_new, dut.spi_ctrl_we); dut.spi_ctrl_new, dut.spi_ctrl_we);
$display(""); $display("");
$display("spi_tx_data_new: 0x%1x, spi_tx_data_nxt: 0x%1x, spi_tx_data_we: 0x%1x", $display("spi_tx_data_new: 0x%1x, spi_tx_data_nxt: 0x%1x, spi_tx_data_we: 0x%1x",
dut.spi_tx_data_new, dut.spi_tx_data_nxt, dut.spi_tx_data_we); dut.spi_tx_data_new, dut.spi_tx_data_nxt, dut.spi_tx_data_we);
$display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x", $display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x", dut.spi_tx_data_reg,
dut.spi_tx_data_reg, dut.spi_tx_data_new); dut.spi_tx_data_new);
$display(""); $display("");
$display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x", $display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x", dut.spi_rx_data_nxt,
dut.spi_rx_data_nxt, dut.spi_rx_data_we); dut.spi_rx_data_we);
$display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x", $display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x", dut.spi_rx_data_reg,
dut.spi_rx_data_reg, dut.spi_rx_data_new); dut.spi_rx_data_new);
$display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x", $display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x", dut.spi_rx_data_reg[0],
dut.spi_rx_data_reg[0], dut.spi_rx_data_new[0]); dut.spi_rx_data_new[0]);
$display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x", $display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x", dut.spi_rx_data_reg[1],
dut.spi_rx_data_reg[1], dut.spi_rx_data_new[1]); dut.spi_rx_data_new[1]);
$display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x", $display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x", dut.spi_rx_data_reg[2],
dut.spi_rx_data_reg[2], dut.spi_rx_data_new[2]); dut.spi_rx_data_new[2]);
$display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x", $display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x", dut.spi_rx_data_reg[3],
dut.spi_rx_data_reg[3], dut.spi_rx_data_new[3]); dut.spi_rx_data_new[3]);
$display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x", $display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x", dut.spi_rx_data_reg[4],
dut.spi_rx_data_reg[4], dut.spi_rx_data_new[4]); dut.spi_rx_data_new[4]);
$display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x", $display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x", dut.spi_rx_data_reg[5],
dut.spi_rx_data_reg[5], dut.spi_rx_data_new[5]); dut.spi_rx_data_new[5]);
$display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x", $display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x", dut.spi_rx_data_reg[6],
dut.spi_rx_data_reg[6], dut.spi_rx_data_new[6]); dut.spi_rx_data_new[6]);
$display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x", $display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x", dut.spi_rx_data_reg[7],
dut.spi_rx_data_reg[7], dut.spi_rx_data_new[7]); dut.spi_rx_data_new[7]);
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
@ -214,12 +208,10 @@ module tb_tk1_spi_master();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("--- All %02d test cases completed successfully", tc_ctr); $display("--- All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.", $display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr); tc_ctr, error_ctr);
end end
@ -353,7 +345,8 @@ module tb_tk1_spi_master();
integer i; integer i;
if (verbose) begin if (verbose) begin
$display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes, address); $display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes,
address);
end end
#(2 * CLK_PERIOD); #(2 * CLK_PERIOD);
@ -695,8 +688,7 @@ module tb_tk1_spi_master();
//---------------------------------------------------------------- //----------------------------------------------------------------
// tk1_spi_master_test // tk1_spi_master_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : tk1_spi_master_test
begin : tk1_spi_master_test
$display(""); $display("");
$display(" -= Testbench for tk1_spi_master started =-"); $display(" -= Testbench for tk1_spi_master started =-");
$display(" ======================================="); $display(" =======================================");

3
hw/application_fpga/core/tk1/tb/udi_rom_sim.v
View file

@ -19,8 +19,7 @@ module udi_rom (
reg [31 : 0] tmp_data; reg [31 : 0] tmp_data;
assign data = tmp_data; assign data = tmp_data;
always @* always @* begin : addr_mux
begin : addr_mux
if (addr) begin if (addr) begin
tmp_data = 32'h04050607; tmp_data = 32'h04050607;
end end

12
hw/application_fpga/core/touch_sense/rtl/touch_sense.v
View file

@ -74,8 +74,7 @@ module touch_sense(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
touch_sense_ctrl_reg <= CTRL_IDLE; touch_sense_ctrl_reg <= CTRL_IDLE;
touch_event_sample0_reg <= 1'h0; touch_event_sample0_reg <= 1'h0;
@ -101,8 +100,7 @@ module touch_sense(
//---------------------------------------------------------------- //----------------------------------------------------------------
// api // api
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api
api_clear_event = 1'h0; api_clear_event = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;
tmp_ready = 1'h0; tmp_ready = 1'h0;
@ -128,8 +126,7 @@ module touch_sense(
//---------------------------------------------------------------- //----------------------------------------------------------------
// touch_event_reg_logic // touch_event_reg_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : touch_event_reg_logic
begin : touch_event_reg_logic
touch_event_new = 1'h0; touch_event_new = 1'h0;
touch_event_we = 1'h0; touch_event_we = 1'h0;
@ -148,8 +145,7 @@ module touch_sense(
//---------------------------------------------------------------- //----------------------------------------------------------------
// touch_sense_ctrl // touch_sense_ctrl
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : touch_sense_ctrl
begin : touch_sense_ctrl
touch_event_set = 1'h0; touch_event_set = 1'h0;
touch_event_rst = 1'h0; touch_event_rst = 1'h0;
touch_sense_ctrl_new = CTRL_IDLE; touch_sense_ctrl_new = CTRL_IDLE;

30
hw/application_fpga/core/touch_sense/tb/tb_touch_sense.v
View file

@ -68,8 +68,7 @@ module tb_touch_sense();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -81,12 +80,10 @@ module tb_touch_sense();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (tb_monitor) if (tb_monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -129,12 +126,10 @@ module tb_touch_sense();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("--- All %02d test cases completed successfully", tc_ctr); $display("--- All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.", $display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr); tc_ctr, error_ctr);
end end
@ -170,11 +165,9 @@ module tb_touch_sense();
// //
// Write the given word to the DUT using the DUT interface. // Write the given word to the DUT using the DUT interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
task write_word(input [7 : 0] address, task write_word(input [7 : 0] address, input [31 : 0] word);
input [31 : 0] word);
begin
if (DEBUG)
begin begin
if (DEBUG) begin
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("--- Writing 0x%08x to 0x%02x.", word, address);
$display(""); $display("");
end end
@ -205,8 +198,7 @@ module tb_touch_sense();
read_data = tb_read_data; read_data = tb_read_data;
tb_cs = 0; tb_cs = 0;
if (DEBUG) if (DEBUG) begin
begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display(""); $display("");
end end
@ -222,8 +214,7 @@ module tb_touch_sense();
task wait_ready; task wait_ready;
begin : wready begin : wready
read_word(ADDR_STATUS); read_word(ADDR_STATUS);
while (read_data == 0) while (read_data == 0) read_word(ADDR_STATUS);
read_word(ADDR_STATUS);
end end
endtask // wait_ready endtask // wait_ready
@ -285,8 +276,7 @@ module tb_touch_sense();
//---------------------------------------------------------------- //----------------------------------------------------------------
// touch_sense_test // touch_sense_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : timer_test
begin : timer_test
$display(""); $display("");
$display(" -= Testbench for touch_sense started =-"); $display(" -= Testbench for touch_sense started =-");
$display(" ===================================="); $display(" ====================================");

33
hw/application_fpga/core/trng/rtl/rosc.v
View file

@ -111,13 +111,23 @@ module rosc(
//---------------------------------------------------------------- //----------------------------------------------------------------
genvar i; genvar i;
generate generate
for(i = 0 ; i < NUM_ROSC ; i = i + 1) for (i = 0; i < NUM_ROSC; i = i + 1) begin : oscillators
begin: oscillators
/* verilator lint_off PINMISSING */ /* verilator lint_off PINMISSING */
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_f (.I0(f[i]), .O(f[i])); (* keep *)
SB_LUT4 #(
.LUT_INIT(16'h1)
) osc_inv_f (
.I0(f[i]),
.O (f[i])
);
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_g (.I0(g[i]), .O(g[i])); (* keep *) SB_LUT4 #(
.LUT_INIT(16'h1)
) osc_inv_g (
.I0(g[i]),
.O (g[i])
);
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
/* verilator lint_on PINMISSING */ /* verilator lint_on PINMISSING */
end end
@ -127,8 +137,7 @@ module rosc(
//--------------------------------------------------------------- //---------------------------------------------------------------
// reg_update // reg_update
//--------------------------------------------------------------- //---------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
cycle_ctr_reg <= 16'h0; cycle_ctr_reg <= 16'h0;
bit_ctr_reg <= 8'h0; bit_ctr_reg <= 8'h0;
@ -174,8 +183,7 @@ module rosc(
// //
// The interface command decoding logic. // The interface command decoding logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api
bit_ctr_rst = 1'h0; bit_ctr_rst = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;
tmp_ready = 1'h0; tmp_ready = 1'h0;
@ -200,8 +208,7 @@ module rosc(
//---------------------------------------------------------------- //----------------------------------------------------------------
// bit_ctr_logic // bit_ctr_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : bit_ctr_logic
begin : bit_ctr_logic
bit_ctr_new = 8'h0; bit_ctr_new = 8'h0;
bit_ctr_we = 1'h0; bit_ctr_we = 1'h0;
data_ready_new = 1'h0; data_ready_new = 1'h0;
@ -228,8 +235,7 @@ module rosc(
//---------------------------------------------------------------- //----------------------------------------------------------------
// cycle_ctr_logic // cycle_ctr_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : cycle_ctr_logic
begin : cycle_ctr_logic
cycle_ctr_new = cycle_ctr_reg + 1'h1; cycle_ctr_new = cycle_ctr_reg + 1'h1;
cycle_ctr_done = 1'h0; cycle_ctr_done = 1'h0;
@ -246,8 +252,7 @@ module rosc(
//---------------------------------------------------------------- //----------------------------------------------------------------
// rosc_ctrl_logic // rosc_ctrl_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rosc_ctrl_logic
begin : rosc_ctrl_logic
reg xor_f; reg xor_f;
reg xor_g; reg xor_g;
reg xor_sample1; reg xor_sample1;

28
hw/application_fpga/core/trng/tb/tb_trng.v
View file

@ -68,8 +68,7 @@ module tb_trng();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -81,12 +80,10 @@ module tb_trng();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (tb_monitor) if (tb_monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -139,12 +136,10 @@ module tb_trng();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("--- All %02d test cases completed successfully", tc_ctr); $display("--- All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.", $display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr); tc_ctr, error_ctr);
end end
@ -195,13 +190,13 @@ module tb_trng();
#(CLK_HALF_PERIOD); #(CLK_HALF_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
if (DEBUG) if (DEBUG) begin
begin
if (read_data == expected) begin if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin end
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", else begin
read_data, address, expected); $display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1; error_ctr = error_ctr + 1;
end end
$display(""); $display("");
@ -230,8 +225,7 @@ module tb_trng();
//---------------------------------------------------------------- //----------------------------------------------------------------
// trng_test // trng_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : trng_test
begin : trng_test
$display(""); $display("");
$display(" -= Testbench for trng started =-"); $display(" -= Testbench for trng started =-");
$display(" ============================"); $display(" ============================");

6
hw/application_fpga/core/uart/rtl/uart.v
View file

@ -182,8 +182,7 @@ module uart(
// All registers are positive edge triggered with synchronous // All registers are positive edge triggered with synchronous
// active low reset. // active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update
if (!reset_n) begin if (!reset_n) begin
bit_rate_reg <= DEFAULT_BIT_RATE; bit_rate_reg <= DEFAULT_BIT_RATE;
data_bits_reg <= DEFAULT_DATA_BITS; data_bits_reg <= DEFAULT_DATA_BITS;
@ -211,8 +210,7 @@ module uart(
// The core API that allows an internal host to control the // The core API that allows an internal host to control the
// core functionality. // core functionality.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin: api
// Default assignments. // Default assignments.
bit_rate_we = 1'h0; bit_rate_we = 1'h0;
data_bits_we = 1'h0; data_bits_we = 1'h0;

21
hw/application_fpga/core/uart/rtl/uart_core.v
View file

@ -169,8 +169,7 @@ module uart_core(
// All registers are positive edge triggered with // All registers are positive edge triggered with
// synchronous active low reset. // synchronous active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update
if (!reset_n) begin if (!reset_n) begin
rxd0_reg <= 1'b0; rxd0_reg <= 1'b0;
rxd_reg <= 1'b0; rxd_reg <= 1'b0;
@ -245,8 +244,7 @@ module uart_core(
// Bit counter for receiving data on the external // Bit counter for receiving data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rxd_bit_ctr
begin: rxd_bit_ctr
rxd_bit_ctr_new = 4'h0; rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b0; rxd_bit_ctr_we = 1'b0;
@ -268,8 +266,7 @@ module uart_core(
// Bitrate counter for receiving data on the external // Bitrate counter for receiving data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rxd_bitrate_ctr
begin: rxd_bitrate_ctr
rxd_bitrate_ctr_new = 16'h0; rxd_bitrate_ctr_new = 16'h0;
rxd_bitrate_ctr_we = 1'h0; rxd_bitrate_ctr_we = 1'h0;
@ -292,8 +289,7 @@ module uart_core(
// Bit counter for transmitting data on the external // Bit counter for transmitting data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : txd_bit_ctr
begin: txd_bit_ctr
txd_bit_ctr_new = 4'h0; txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h0; txd_bit_ctr_we = 1'h0;
@ -315,8 +311,7 @@ module uart_core(
// Bitrate counter for transmitting data on the external // Bitrate counter for transmitting data on the external
// serial interface. // serial interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : txd_bitrate_ctr
begin: txd_bitrate_ctr
txd_bitrate_ctr_new = 16'h0; txd_bitrate_ctr_new = 16'h0;
txd_bitrate_ctr_we = 0; txd_bitrate_ctr_we = 0;
@ -340,8 +335,7 @@ module uart_core(
// if required checks parity and store correct data into // if required checks parity and store correct data into
// the rx buffer. // the rx buffer.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : external_rx_engine
begin: external_rx_engine
rxd_bit_ctr_rst = 0; rxd_bit_ctr_rst = 0;
rxd_bit_ctr_inc = 0; rxd_bit_ctr_inc = 0;
rxd_bitrate_ctr_rst = 0; rxd_bitrate_ctr_rst = 0;
@ -432,8 +426,7 @@ module uart_core(
// Logic that implements the transmit engine towards // Logic that implements the transmit engine towards
// the external interface. // the external interface.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : external_tx_engine
begin: external_tx_engine
txd_new = 0; txd_new = 0;
txd_we = 0; txd_we = 0;
txd_byte_new = 0; txd_byte_new = 0;

12
hw/application_fpga/core/uart/rtl/uart_fifo.v
View file

@ -95,8 +95,7 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin: reg_update
if (!reset_n) begin if (!reset_n) begin
in_ptr_reg <= 9'h0; in_ptr_reg <= 9'h0;
out_ptr_reg <= 9'h0; out_ptr_reg <= 9'h0;
@ -128,8 +127,7 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// byte_ctr // byte_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : byte_ctr
begin : byte_ctr
fifo_empty = 1'h0; fifo_empty = 1'h0;
fifo_full = 1'h0; fifo_full = 1'h0;
byte_ctr_new = 9'h0; byte_ctr_new = 9'h0;
@ -158,8 +156,7 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// in_logic // in_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : in_logic
begin : in_logic
fifo_mem_we = 1'h0; fifo_mem_we = 1'h0;
in_ack_new = 1'h0; in_ack_new = 1'h0;
byte_ctr_inc = 1'h0; byte_ctr_inc = 1'h0;
@ -179,8 +176,7 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// out_logic // out_logic
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : out_logic
begin : out_logic
byte_ctr_dec = 1'h0; byte_ctr_dec = 1'h0;
out_ptr_we = 1'h0; out_ptr_we = 1'h0;

58
hw/application_fpga/core/uart/tb/tb_uart.v
View file

@ -99,8 +99,7 @@ module tb_uart();
// //
// Clock generator process. // Clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk; #CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -108,17 +107,14 @@ module tb_uart();
//---------------------------------------------------------------- //----------------------------------------------------------------
// sys_monitor // sys_monitor
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
#(CLK_PERIOD); #(CLK_PERIOD);
if (DEBUG) if (DEBUG) begin
begin
dump_rx_state(); dump_rx_state();
dump_tx_state(); dump_tx_state();
$display(""); $display("");
end end
if (VERBOSE) if (VERBOSE) begin
begin
$display("cycle: 0x%016x", cycle_ctr); $display("cycle: 0x%016x", cycle_ctr);
end end
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
@ -130,16 +126,13 @@ module tb_uart();
// //
// Observes what happens on the dut tx port and reports it. // Observes what happens on the dut tx port and reports it.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : tx_monitor
begin : tx_monitor if ((!tb_txd) && txd_state) begin
if ((!tb_txd) && txd_state)
begin
$display("txd going low."); $display("txd going low.");
txd_state = 0; txd_state = 0;
end end
if (tb_txd && (!txd_state)) if (tb_txd && (!txd_state)) begin
begin
$display("txd going high"); $display("txd going high");
txd_state = 1; txd_state = 1;
end end
@ -156,24 +149,21 @@ module tb_uart();
$display("State of DUT"); $display("State of DUT");
$display("------------"); $display("------------");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("rxd = 0x%01x, txd = 0x%01x,", $display("rxd = 0x%01x, txd = 0x%01x,", dut.core.rxd, dut.core.txd);
dut.core.rxd, dut.core.txd);
$display(""); $display("");
$display("Sample and data registers:"); $display("Sample and data registers:");
$display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x", $display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x", dut.core.rxd_reg, dut.core.rxd_byte_reg);
dut.core.rxd_reg, dut.core.rxd_byte_reg);
$display(""); $display("");
$display("Counters:"); $display("Counters:");
$display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x", $display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x", dut.core.rxd_bit_ctr_reg,
dut.core.rxd_bit_ctr_reg, dut.core.rxd_bitrate_ctr_reg); dut.core.rxd_bitrate_ctr_reg);
$display(""); $display("");
$display("Control signals and FSM state:"); $display("Control signals and FSM state:");
$display("erx_ctrl_reg = 0x%02x", $display("erx_ctrl_reg = 0x%02x", dut.core.erx_ctrl_reg);
dut.core.erx_ctrl_reg);
$display(""); $display("");
end end
endtask // dump_dut_state endtask // dump_dut_state
@ -187,7 +177,8 @@ module tb_uart();
//---------------------------------------------------------------- //----------------------------------------------------------------
task dump_rx_state; task dump_rx_state;
begin begin
$display("rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x", $display(
"rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x",
dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg, dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg,
dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg); dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg);
end end
@ -262,8 +253,7 @@ module tb_uart();
#(CLK_PERIOD * dut.DEFAULT_BIT_RATE); #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
// Send the bits LSB first. // Send the bits LSB first.
for (i = 0 ; i < 8 ; i = i + 1) for (i = 0; i < 8; i = i + 1) begin
begin
$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]); $display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
tb_rxd = data[i]; tb_rxd = data[i];
#(CLK_PERIOD * dut.DEFAULT_BIT_RATE); #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
@ -290,13 +280,10 @@ module tb_uart();
transmit_byte(data); transmit_byte(data);
if (dut.core.rxd_byte_reg == data) if (dut.core.rxd_byte_reg == data) begin
begin $display("*** Correct data: 0x%01x captured by the dut.", dut.core.rxd_byte_reg);
$display("*** Correct data: 0x%01x captured by the dut.",
dut.core.rxd_byte_reg);
end end
else else begin
begin
$display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.", $display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
dut.core.rxd_byte_reg, data); dut.core.rxd_byte_reg, data);
error_ctr = error_ctr + 1; error_ctr = error_ctr + 1;
@ -327,12 +314,10 @@ module tb_uart();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("*** All %02d test cases completed successfully", tc_ctr); $display("*** All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("*** %02d test cases did not complete successfully.", error_ctr); $display("*** %02d test cases did not complete successfully.", error_ctr);
end end
end end
@ -343,8 +328,7 @@ module tb_uart();
// uart_test // uart_test
// The main test functionality. // The main test functionality.
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : uart_test
begin : uart_test
$display(" -- Testbench for uart core started --"); $display(" -- Testbench for uart core started --");
init_sim(); init_sim();

8
hw/application_fpga/core/uds/rtl/uds.v
View file

@ -61,13 +61,12 @@ module uds(
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update // reg_update
//---------------------------------------------------------------- //----------------------------------------------------------------
always @ (posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
integer i; integer i;
if (!reset_n) begin if (!reset_n) begin
for (i = 0; i < 8; i = i + 1) begin for (i = 0; i < 8; i = i + 1) begin
uds_rd_reg[i] <= 1'h0;; uds_rd_reg[i] <= 1'h0;
end end
end end
else begin else begin
@ -83,8 +82,7 @@ module uds(
// //
// The interface command decoding logic. // The interface command decoding logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : api
begin : api
uds_rd_we = 1'h0; uds_rd_we = 1'h0;
tmp_ready = 1'h0; tmp_ready = 1'h0;

8
hw/application_fpga/core/uds/rtl/uds_rom.v
View file

@ -23,11 +23,13 @@ module uds_rom(
generate generate
genvar ii; genvar ii;
for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts for (ii = 0; ii < 32; ii = ii + 1'b1) begin : luts
(* uds_rom_idx=ii, keep *) SB_LUT4 (* uds_rom_idx=ii, keep *) SB_LUT4 #(
#(
.LUT_INIT({8'ha6 ^ ii[7:0], 8'h00}) .LUT_INIT({8'ha6 ^ ii[7:0], 8'h00})
) lut_i ( ) lut_i (
.I0(addr[0]), .I1(addr[1]), .I2(addr[2]), .I3(re), .I0(addr[0]),
.I1(addr[1]),
.I2(addr[2]),
.I3(re),
.O (data[ii]) .O (data[ii])
); );
end end

31
hw/application_fpga/core/uds/tb/tb_uds.v
View file

@ -63,8 +63,7 @@ module tb_uds();
// //
// Always running clock generator process. // Always running clock generator process.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : clk_gen
begin : clk_gen
#CLK_HALF_PERIOD; #CLK_HALF_PERIOD;
tb_clk = !tb_clk; tb_clk = !tb_clk;
end // clk_gen end // clk_gen
@ -76,12 +75,10 @@ module tb_uds();
// An always running process that creates a cycle counter and // An always running process that creates a cycle counter and
// conditionally displays information about the DUT. // conditionally displays information about the DUT.
//---------------------------------------------------------------- //----------------------------------------------------------------
always always begin : sys_monitor
begin : sys_monitor
cycle_ctr = cycle_ctr + 1; cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD); #(CLK_PERIOD);
if (tb_monitor) if (tb_monitor) begin
begin
dump_dut_state(); dump_dut_state();
end end
end end
@ -105,7 +102,8 @@ module tb_uds();
$display("Internal state:"); $display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data); $display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
for (i = 0; i < 8; i = i + 1) begin for (i = 0; i < 8; i = i + 1) begin
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]); $display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i,
dut.uds_rd_reg[i]);
end end
$display(""); $display("");
@ -136,12 +134,10 @@ module tb_uds();
//---------------------------------------------------------------- //----------------------------------------------------------------
task display_test_result; task display_test_result;
begin begin
if (error_ctr == 0) if (error_ctr == 0) begin
begin
$display("--- All %02d test cases completed successfully", tc_ctr); $display("--- All %02d test cases completed successfully", tc_ctr);
end end
else else begin
begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.", $display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr); tc_ctr, error_ctr);
end end
@ -191,13 +187,13 @@ module tb_uds();
#(CLK_HALF_PERIOD); #(CLK_HALF_PERIOD);
tb_cs = 1'h0; tb_cs = 1'h0;
if (DEBUG) if (DEBUG) begin
begin
if (read_data == expected) begin if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("--- Reading 0x%08x from 0x%02x.", read_data, address);
end else begin end
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", else begin
read_data, address, expected); $display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", read_data,
address, expected);
error_ctr = error_ctr + 1; error_ctr = error_ctr + 1;
end end
$display(""); $display("");
@ -306,8 +302,7 @@ module tb_uds();
//---------------------------------------------------------------- //----------------------------------------------------------------
// uds_test // uds_test
//---------------------------------------------------------------- //----------------------------------------------------------------
initial initial begin : uds_test
begin : uds_test
$display(""); $display("");
$display(" -= Testbench for uds started =-"); $display(" -= Testbench for uds started =-");
$display(" ==========================="); $display(" ===========================");

11
hw/application_fpga/rtl/application_fpga.v
View file

@ -153,8 +153,9 @@ module application_fpga(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Module instantiations. // Module instantiations.
//---------------------------------------------------------------- //----------------------------------------------------------------
clk_reset_gen #(.RESET_CYCLES(200)) clk_reset_gen #(
reset_gen_inst( .RESET_CYCLES(200)
) reset_gen_inst (
.sys_reset(tk1_system_reset), .sys_reset(tk1_system_reset),
.clk(clk), .clk(clk),
.rst_n(reset_n) .rst_n(reset_n)
@ -359,8 +360,7 @@ module application_fpga(
// Reg_update. // Reg_update.
// Posedge triggered with synchronous, active low reset. // Posedge triggered with synchronous, active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
muxed_rdata_reg <= 32'h0; muxed_rdata_reg <= 32'h0;
muxed_ready_reg <= 1'h0; muxed_ready_reg <= 1'h0;
@ -377,8 +377,7 @@ module application_fpga(
// cpu_mem_ctrl // cpu_mem_ctrl
// CPU memory decode and control logic. // CPU memory decode and control logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : cpu_mem_ctrl
begin : cpu_mem_ctrl
reg [1 : 0] area_prefix; reg [1 : 0] area_prefix;
reg [5 : 0] core_prefix; reg [5 : 0] core_prefix;

14
hw/application_fpga/tb/application_fpga_vsim.v
View file

@ -169,8 +169,12 @@ module application_fpga(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Module instantiations. // Module instantiations.
//---------------------------------------------------------------- //----------------------------------------------------------------
reset_gen #(.RESET_CYCLES(200)) reset_gen #(
reset_gen_inst(.clk(clk), .rst_n(reset_n)); .RESET_CYCLES(200)
) reset_gen_inst (
.clk (clk),
.rst_n(reset_n)
);
picorv32 #( picorv32 #(
@ -324,8 +328,7 @@ module application_fpga(
// Reg_update. // Reg_update.
// Posedge triggered with synchronous, active low reset. // Posedge triggered with synchronous, active low reset.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
if (!reset_n) begin if (!reset_n) begin
muxed_ready_reg <= 1'h0; muxed_ready_reg <= 1'h0;
muxed_rdata_reg <= 32'h0; muxed_rdata_reg <= 32'h0;
@ -342,8 +345,7 @@ module application_fpga(
// cpu_mem_ctrl // cpu_mem_ctrl
// CPU memory decode and control logic. // CPU memory decode and control logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : cpu_mem_ctrl
begin : cpu_mem_ctrl
reg [1 : 0] area_prefix; reg [1 : 0] area_prefix;
reg [5 : 0] core_prefix; reg [5 : 0] core_prefix;

14
hw/application_fpga/tb/reset_gen_vsim.v
View file

@ -13,8 +13,9 @@
`default_nettype none `default_nettype none
module reset_gen #(parameter RESET_CYCLES = 200) module reset_gen #(
( parameter RESET_CYCLES = 200
) (
input wire clk, input wire clk,
output wire rst_n output wire rst_n
); );
@ -40,20 +41,17 @@ module reset_gen #(parameter RESET_CYCLES = 200)
//---------------------------------------------------------------- //----------------------------------------------------------------
// reg_update. // reg_update.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) always @(posedge clk) begin : reg_update
begin : reg_update
rst_n_reg <= rst_n_new; rst_n_reg <= rst_n_new;
if (rst_ctr_we) if (rst_ctr_we) rst_ctr_reg <= rst_ctr_new;
rst_ctr_reg <= rst_ctr_new;
end end
//---------------------------------------------------------------- //----------------------------------------------------------------
// rst_logic. // rst_logic.
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @* begin : rst_logic
begin : rst_logic
rst_n_new = 1'h1; rst_n_new = 1'h1;
rst_ctr_new = 8'h0; rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0; rst_ctr_we = 1'h0;