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@ -64,7 +64,7 @@
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35,
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36
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],
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"visible_layers": "0021000_7ffffff9",
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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},
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"meta": {
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@ -490,32 +490,7 @@
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},
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": [
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{
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"netclass": "power",
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"pattern": "+1V2"
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},
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{
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"netclass": "power",
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"pattern": "+2V5"
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},
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{
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"netclass": "power",
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"pattern": "+3V3"
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},
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{
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"netclass": "power",
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"pattern": "+5V"
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},
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{
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"netclass": "power",
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"pattern": "/Application FPGA/APP_+1.2_PLL"
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},
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{
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"netclass": "power",
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"pattern": "GND"
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}
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]
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"netclass_patterns": []
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},
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"pcbnew": {
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"last_paths": {
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