Restore start and stop bits, but clarify in documenation

doc/system_description/software.md

@@ -310,8 +310,9 @@ Assigned core prefixes:
 |--------------------|------|------------|--------|---------|-----------|-----------------------------------------------------------------------|
 | `TRNG_STATUS`      | r    | r          |        |         |           | Non-zero when an entropy word is available.                           |
 | `TRNG_ENTROPY`     | r    | r          | 4B     |         |           | Entropy word. Reading a word will clear status.                       |
-| `TIMER_CTRL`       | r/w  | r/w        |        |         |           | If bit zero is set timer is running.                                  |
+| `TIMER_CTRL`       | r/w  | r/w        |        |         |           | If bit zero is set when status is set, the timer will start running.  |
-| `TIMER_STATUS`     | r    | r          |        |         |           | Bit zero is set if ready to start running.                            |
+|                    |      |            |        |         |           | If bit one is set when status is not set, the timer will stop running.|
+| `TIMER_STATUS`     | r    | r          |        |         |           | If bit zero is set, the timer is ready to start running.              |
 | `TIMER_PRESCALER`  | r/w  | r/w        | 4B     |         |           | Prescaler init value. Write blocked when running.                     |
 | `TIMER_TIMER`      | r/w  | r/w        | 4B     |         |           | Timer init or current value when running. Write blocked when running. |
 | `UDS_START`        | r[^2]| invisible  | 4B     | u8[32]  |           | First word of Unique Device Secret key.                               |

hw/application_fpga/core/timer/rtl/timer.v

@@ -31,7 +31,8 @@ module timer(
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
   localparam ADDR_CTRL       = 8'h08;
-  localparam CTRL_RUN_BIT    = 0;
+  localparam CTRL_START_BIT  = 0;
+  localparam CTRL_STOP_BIT   = 1;
 
   localparam ADDR_STATUS      = 8'h09;
   localparam STATUS_READY_BIT = 0;
@@ -49,8 +50,11 @@ module timer(
   reg [31 : 0] timer_reg;
   reg          timer_we;
 
-  reg          run_reg;
+  reg          start_reg;
-  reg          run_we;
+  reg          start_new;
+
+  reg          stop_reg;
+  reg          stop_new;
 
 
   //----------------------------------------------------------------
@@ -76,9 +80,12 @@ module timer(
   timer_core core(
                   .clk(clk),
                   .reset_n(reset_n),
+
                   .prescaler_init(prescaler_reg),
                   .timer_init(timer_reg),
-                  .run(run_reg),
+                  .start(start_reg),
+                  .stop(stop_reg),
+
 		  .curr_timer(core_curr_timer),
                   .ready(core_ready)
                  );
@@ -90,15 +97,14 @@ module timer(
   always @ (posedge clk)
     begin : reg_update
       if (!reset_n) begin
-	run_reg       <= 1'h0;
+	start_reg     <= 1'h0;
+	stop_reg      <= 1'h0;
 	prescaler_reg <= 32'h0;
 	timer_reg     <= 32'h0;
       end
-
       else begin
-	if (run_we) begin
+	start_reg <= start_new;
-	  run_reg <= write_data[CTRL_RUN_BIT];
+	stop_reg  <= stop_new;
-	end
 
 	if (prescaler_we) begin
 	  prescaler_reg <= write_data;
@@ -118,7 +124,8 @@ module timer(
   //----------------------------------------------------------------
   always @*
     begin : api
-      run_we        = 1'h0;
+      start_new     = 1'h0;
+      stop_new      = 1'h0;
       prescaler_we  = 1'h0;
       timer_we      = 1'h0;
       tmp_read_data = 32'h0;
@@ -129,7 +136,8 @@ module timer(
 
         if (we) begin
           if (address == ADDR_CTRL) begin
-	    run_we = 1'h1;
+	    start_new = write_data[CTRL_START_BIT];
+	    stop_new  = write_data[CTRL_STOP_BIT];
 	  end
 
 	  if (core_ready) begin
@@ -144,10 +152,6 @@ module timer(
         end
 
         else begin
-	  if (address == ADDR_CTRL) begin
-	    tmp_read_data = {31'h0, run_reg};
-	  end
-
 	  if (address == ADDR_STATUS) begin
 	    tmp_read_data = {31'h0, core_ready};
 	  end

hw/application_fpga/core/timer/rtl/timer_core.v

@@ -19,10 +19,10 @@ module timer_core(
 
                   input wire [31 : 0]  prescaler_init,
                   input wire [31 : 0]  timer_init,
-                  input wire           run,
+                  input wire           start,
+                  input wire           stop,
 
                   output wire [31 : 0] curr_timer,
-
                   output wire          ready
                   );
 
@@ -153,7 +153,7 @@ module timer_core(
 
       case (core_ctrl_reg)
         CTRL_IDLE: begin
-          if (run)
+          if (start)
             begin
               ready_new     = 1'h0;
               ready_we      = 1'h1;
@@ -166,7 +166,7 @@ module timer_core(
 
 
 	CTRL_PRESCALER: begin
-	  if (!run) begin
+	  if (stop) begin
             ready_new     = 1'h1;
             ready_we      = 1'h1;
             core_ctrl_new = CTRL_IDLE;
@@ -187,7 +187,7 @@ module timer_core(
 
 
 	CTRL_TIMER: begin
-	  if (!run) begin
+	  if (stop) begin
             ready_new     = 1'h1;
             ready_we      = 1'h1;
             core_ctrl_new = CTRL_IDLE;

hw/application_fpga/fw/mta1_mkdf_mem.h

@@ -43,7 +43,8 @@ enum {
     MTA1_MKDF_MMIO_TRNG_ENTROPY     = MTA1_MKDF_MMIO_TRNG_BASE | 0x80,
 
     MTA1_MKDF_MMIO_TIMER_CTRL       = MTA1_MKDF_MMIO_TIMER_BASE | 0x20,
-    MTA1_MKDF_MMIO_TIMER_CTRL_RUN_BIT = 0,
+    MTA1_MKDF_MMIO_TIMER_CTRL_START_BIT = 0,
+    MTA1_MKDF_MMIO_TIMER_CTRL_STOP_BIT  = 1,
     MTA1_MKDF_MMIO_TIMER_STATUS     = MTA1_MKDF_MMIO_TIMER_BASE | 0x24,
     MTA1_MKDF_MMIO_TIMER_STATUS_READY_BIT = 0,
     MTA1_MKDF_MMIO_TIMER_PRESCALER  = MTA1_MKDF_MMIO_TIMER_BASE | 0x28,