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Change "rosc" references to "trng"

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Jonas Thörnblad 2024-11-13 16:09:52 +01:00
parent 2364466a9e
commit 1b3bae334a
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GPG key ID: 2D318AD00A326F95
4 changed files with 29 additions and 29 deletions
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44
hw/application_fpga/core/trng/rtl/trng.v
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@ -1,6 +1,6 @@
//======================================================================
//
// rosc.v
// trng.v
// ------
// Digital ring oscillator based entropy generator.
// Use this as a source of entropy, for example as seeds.
@ -16,7 +16,7 @@
`default_nettype none
module rosc (
module trng (
input wire clk,
input wire reset_n,
@ -78,9 +78,9 @@ module rosc (
reg data_ready_new;
reg data_ready_we;
reg [ 1 : 0] rosc_ctrl_reg;
reg [ 1 : 0] rosc_ctrl_new;
reg rosc_ctrl_we;
reg [ 1 : 0] trng_ctrl_reg;
reg [ 1 : 0] trng_ctrl_new;
reg trng_ctrl_we;
//----------------------------------------------------------------
// Wires.
@ -145,7 +145,7 @@ module rosc (
sample2_reg <= 2'h0;
entropy_reg <= 32'h0;
data_ready_reg <= 1'h0;
rosc_ctrl_reg <= CTRL_SAMPLE1;
trng_ctrl_reg <= CTRL_SAMPLE1;
end
else begin
@ -171,8 +171,8 @@ module rosc (
data_ready_reg <= data_ready_new;
end
if (rosc_ctrl_we) begin
rosc_ctrl_reg <= rosc_ctrl_new;
if (trng_ctrl_we) begin
trng_ctrl_reg <= trng_ctrl_new;
end
end
end
@ -250,9 +250,9 @@ module rosc (
//----------------------------------------------------------------
// rosc_ctrl_logic
// trng_ctrl_logic
//----------------------------------------------------------------
always @* begin : rosc_ctrl_logic
always @* begin : trng_ctrl_logic
reg xor_f;
reg xor_g;
reg xor_sample1;
@ -263,8 +263,8 @@ module rosc (
entropy_we = 1'h0;
cycle_ctr_rst = 1'h0;
bit_ctr_inc = 1'h0;
rosc_ctrl_new = CTRL_SAMPLE1;
rosc_ctrl_we = 1'h0;
trng_ctrl_new = CTRL_SAMPLE1;
trng_ctrl_we = 1'h0;
xor_f = ^f;
xor_g = ^g;
@ -275,14 +275,14 @@ module rosc (
sample2_new = {sample2_reg[0], xor_g};
entropy_new = {entropy_reg[30 : 0], xor_sample1 ^ xor_sample2};
case (rosc_ctrl_reg)
case (trng_ctrl_reg)
CTRL_SAMPLE1: begin
if (cycle_ctr_done) begin
cycle_ctr_rst = 1'h1;
sample1_we = 1'h1;
sample2_we = 1'h1;
rosc_ctrl_new = CTRL_SAMPLE2;
rosc_ctrl_we = 1'h1;
trng_ctrl_new = CTRL_SAMPLE2;
trng_ctrl_we = 1'h1;
end
end
@ -291,25 +291,25 @@ module rosc (
cycle_ctr_rst = 1'h1;
sample1_we = 1'h1;
sample2_we = 1'h1;
rosc_ctrl_new = CTRL_DATA_READY;
rosc_ctrl_we = 1'h1;
trng_ctrl_new = CTRL_DATA_READY;
trng_ctrl_we = 1'h1;
end
end
CTRL_DATA_READY: begin
entropy_we = 1'h1;
bit_ctr_inc = 1'h1;
rosc_ctrl_new = CTRL_SAMPLE1;
rosc_ctrl_we = 1'h1;
trng_ctrl_new = CTRL_SAMPLE1;
trng_ctrl_we = 1'h1;
end
default: begin
end
endcase // case (rosc_ctrl_reg)
endcase // case (trng_ctrl_reg)
end
endmodule // rosc
endmodule // trng
//======================================================================
// EOF rosc.v
// EOF trng.v
//======================================================================

2
hw/application_fpga/core/trng/tb/tb_trng.v
View file

@ -50,7 +50,7 @@ module tb_trng ();
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
rosc dut (
trng dut (
.clk(tb_clk),
.reset_n(tb_reset_n),