Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-12-29 17:36:26 -05:00
Code Issues Packages Projects Releases Wiki Activity

Remove app-accessible debug register from mta1 core

Browse Source
This commit is contained in:
Joachim Strömbergson 2022-10-13 13:51:19 +02:00
parent 51a22dc32c
commit 1b03459ab3
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
2 changed files with 0 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
hw/application_fpga/core/mta1/rtl/mta1.v
View File

@ -61,8 +61,6 @@ module mta1(
localparam ADDR_APP_START = 8'h0c; localparam ADDR_APP_START = 8'h0c;
localparam ADDR_APP_SIZE = 8'h0d; localparam ADDR_APP_SIZE = 8'h0d;
localparam ADDR_DEBUG = 8'h10;
localparam ADDR_CDI_FIRST = 8'h20; localparam ADDR_CDI_FIRST = 8'h20;
localparam ADDR_CDI_LAST = 8'h27; localparam ADDR_CDI_LAST = 8'h27;
@ -102,9 +100,6 @@ module mta1(
reg [31 : 0] app_size_reg; reg [31 : 0] app_size_reg;
reg app_size_we; reg app_size_we;
reg [31 : 0] debug_reg;
reg debug_we;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
@ -163,7 +158,6 @@ module mta1(
gpio4_reg <= 1'h0; gpio4_reg <= 1'h0;
app_start_reg <= 32'h0; app_start_reg <= 32'h0;
app_size_reg <= 32'h0; app_size_reg <= 32'h0;
debug_reg <= 32'h0;
cdi_mem[0] <= 32'h0; cdi_mem[0] <= 32'h0;
cdi_mem[1] <= 32'h0; cdi_mem[1] <= 32'h0;
cdi_mem[2] <= 32'h0; cdi_mem[2] <= 32'h0;
@ -205,10 +199,6 @@ module mta1(
app_size_reg <= write_data; app_size_reg <= write_data;
end end
if (debug_we) begin
debug_reg <= write_data;
end
if (cdi_mem_we) begin if (cdi_mem_we) begin
cdi_mem[address[2 : 0]] <= write_data; cdi_mem[address[2 : 0]] <= write_data;
end end
@ -227,7 +217,6 @@ module mta1(
gpio4_we = 1'h0; gpio4_we = 1'h0;
app_start_we = 1'h0; app_start_we = 1'h0;
app_size_we = 1'h0; app_size_we = 1'h0;
debug_we = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
tmp_read_data = 32'h00000000; tmp_read_data = 32'h00000000;
@ -261,10 +250,6 @@ module mta1(
end end
end end
if (address == ADDR_DEBUG) begin
debug_we = 1'h1;
end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (!switch_app_reg) begin if (!switch_app_reg) begin
cdi_mem_we = 1'h1; cdi_mem_we = 1'h1;
@ -306,10 +291,6 @@ module mta1(
tmp_read_data = app_size_reg; tmp_read_data = app_size_reg;
end end
if (address == ADDR_DEBUG) begin
tmp_read_data = debug_reg;
end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
tmp_read_data = cdi_mem[address[2 : 0]]; tmp_read_data = cdi_mem[address[2 : 0]];
end end

1
hw/application_fpga/fw/mta1_mkdf_mem.h
View File

@ -84,7 +84,6 @@ enum {
MTA1_MKDF_MMIO_MTA1_GPIO4_BIT = 3, MTA1_MKDF_MMIO_MTA1_GPIO4_BIT = 3,
MTA1_MKDF_MMIO_MTA1_APP_ADDR = MTA1_MKDF_MMIO_MTA1_BASE | 0x30, // 0x4000_0000 MTA1_MKDF_MMIO_MTA1_APP_ADDR = MTA1_MKDF_MMIO_MTA1_BASE | 0x30, // 0x4000_0000
MTA1_MKDF_MMIO_MTA1_APP_SIZE = MTA1_MKDF_MMIO_MTA1_BASE | 0x34, MTA1_MKDF_MMIO_MTA1_APP_SIZE = MTA1_MKDF_MMIO_MTA1_BASE | 0x34,
MTA1_MKDF_MMIO_MTA1_DEBUG = MTA1_MKDF_MMIO_MTA1_BASE | 0x40,
MTA1_MKDF_MMIO_MTA1_CDI_FIRST = MTA1_MKDF_MMIO_MTA1_BASE | 0x80, MTA1_MKDF_MMIO_MTA1_CDI_FIRST = MTA1_MKDF_MMIO_MTA1_BASE | 0x80,
MTA1_MKDF_MMIO_MTA1_CDI_LAST = MTA1_MKDF_MMIO_MTA1_BASE | 0x9c, // Address of last 32-bit word of CDI. MTA1_MKDF_MMIO_MTA1_CDI_LAST = MTA1_MKDF_MMIO_MTA1_BASE | 0x9c, // Address of last 32-bit word of CDI.
MTA1_MKDF_MMIO_MTA1_UDI_FIRST = MTA1_MKDF_MMIO_MTA1_BASE | 0xc0, MTA1_MKDF_MMIO_MTA1_UDI_FIRST = MTA1_MKDF_MMIO_MTA1_BASE | 0xc0,