diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
index c8962cb..60200ca 100644
--- a/hw/application_fpga/Makefile
+++ b/hw/application_fpga/Makefile
@@ -48,7 +48,7 @@ TOP_SRC = $(P)/rtl/application_fpga.v
 VERILATOR_TOP_SRC = $(P)/tb/application_fpga_vsim.v
 
 VERILOG_SRCS = \
-	$(P)/rtl/reset_gen.v \
+	$(P)/rtl/clk_reset_gen.v \
 	$(P)/rtl/ram.v \
 	$(P)/rtl/rom.v \
 	$(P)/core/picorv32/rtl/picorv32.v \
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
index 092ec4c..729418d 100644
--- a/hw/application_fpga/core/uart/rtl/uart.v
+++ b/hw/application_fpga/core/uart/rtl/uart.v
@@ -90,9 +90,9 @@ module uart(
   // The default bit rate is based on target clock frequency
   // divided by the bit rate times in order to hit the
   // center of the bits. I.e.
-  // Clock: 12 MHz, 38400 bps
-  // Divisor = 12*10E6 / 38400 = 312
-  localparam DEFAULT_BIT_RATE  = 16'd312;
+  // Clock: 18 MHz, 38400 bps
+  // Divisor = 18*10E6 / 38400 = 468.75 ~ 469
+  localparam DEFAULT_BIT_RATE  = 16'd469;
   localparam DEFAULT_DATA_BITS = 4'h8;
   localparam DEFAULT_STOP_BITS = 2'h1;
 
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index 3bd29aa..ecef4ec 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -139,24 +139,11 @@ module application_fpga(
   wire          fw_app_mode;
 
 
-  //----------------------------------------------------------------
-  // Concurrent assignments.
-  //----------------------------------------------------------------
-
-
   //----------------------------------------------------------------
   // Module instantiations.
   //----------------------------------------------------------------
-  // Use the FPGA internal High Frequency OSCillator as clock source.
-  // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
-  /* verilator lint_off PINMISSING */
-  SB_HFOSC #(.CLKHF_DIV("0b10")
-	     ) u_hfosc (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(clk));
-  /* verilator lint_on PINMISSING */
-
-
-  reset_gen #(.RESET_CYCLES(200))
-    reset_gen_inst(.clk(clk), .rst_n(reset_n));
+  clk_reset_gen #(.RESET_CYCLES(200))
+  reset_gen_inst(.clk(clk), .rst_n(reset_n));
 
 
   picorv32 #(
diff --git a/hw/application_fpga/rtl/reset_gen.v b/hw/application_fpga/rtl/clk_reset_gen.v
similarity index 53%
rename from hw/application_fpga/rtl/reset_gen.v
rename to hw/application_fpga/rtl/clk_reset_gen.v
index 527b9c1..b8a1144 100644
--- a/hw/application_fpga/rtl/reset_gen.v
+++ b/hw/application_fpga/rtl/clk_reset_gen.v
@@ -1,8 +1,11 @@
 //======================================================================
 //
-// reset_gen.v
+// clk_reset_gen.v
 // -----------
-// Reset generator for iCE40 based systems.
+// Clock and reset generator used in the Tillitis Key 1 design.
+// This module instantiate the internal SB_HFOSC clock source in the
+// Lattice ice40 UP device. It then connects it to the PLL, and
+// finally connects the output from the PLL to the global clock net.
 //
 //
 // Author: Joachim Strombergson
@@ -13,11 +16,11 @@
 
 `default_nettype none
 
-module reset_gen #(parameter RESET_CYCLES = 200)
-                 (
-	          input wire  clk,
-                  output wire rst_n
-                 );
+module clk_reset_gen #(parameter RESET_CYCLES = 200)
+  (
+   output wire clk,
+   output wire rst_n
+   );
 
 
   //----------------------------------------------------------------
@@ -30,6 +33,9 @@ module reset_gen #(parameter RESET_CYCLES = 200)
   reg         rst_n_reg = 1'h0;
   reg         rst_n_new;
 
+  wire        hfosc_clk;
+  wire        pll_clk;
+
 
   //----------------------------------------------------------------
   // Concurrent assignment.
@@ -37,6 +43,39 @@ module reset_gen #(parameter RESET_CYCLES = 200)
   assign rst_n = rst_n_reg;
 
 
+  //----------------------------------------------------------------
+  // Core instantiations.
+  //----------------------------------------------------------------
+  // Use the FPGA internal High Frequency OSCillator as clock source.
+  // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
+  /* verilator lint_off PINMISSING */
+  SB_HFOSC #(.CLKHF_DIV("0b10")
+	     ) u_hfosc (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
+  /* verilator lint_on PINMISSING */
+
+
+  // PLL to generate a new clock frequency based on the HFOSC clock.
+  /* verilator lint_off PINMISSING */
+  SB_PLL40_CORE #(
+		  .FEEDBACK_PATH("SIMPLE"),
+		  .DIVR(4'b0000),	// DIVR =  0
+		  .DIVF(7'b0101111),	// DIVF = 47
+		  .DIVQ(3'b101),	// DIVQ =  5
+		  .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+		  ) uut (
+			 .RESETB(1'b1),
+			 .BYPASS(1'b0),
+			 .REFERENCECLK(hfosc_clk),
+			 .PLLOUTCORE(pll_clk)
+			 );
+  /* verilator lint_on PINMISSING */
+
+  // Use a global buffer to distribute the clock.
+  SB_GB SB_GB_i (
+		 .USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
+		 .GLOBAL_BUFFER_OUTPUT (clk)
+		 );
+
   //----------------------------------------------------------------
   // reg_update.
   //----------------------------------------------------------------