From 1a47a2266f4d9b5a3b666823828fafcb5344d376 Mon Sep 17 00:00:00 2001
From: Daniel Jobson <jobson@tillitis.se>
Date: Fri, 17 Oct 2025 10:05:04 +0200
Subject: [PATCH] uart: Make CTS active low, as per the standard

---
 hw/application_fpga/core/uart/README.md       | 5 +++++
 hw/application_fpga/core/uart/rtl/uart.v      | 2 +-
 hw/application_fpga/core/uart/rtl/uart_fifo.v | 6 +++---
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/hw/application_fpga/core/uart/README.md b/hw/application_fpga/core/uart/README.md
index 95c47ea..71743ca 100644
--- a/hw/application_fpga/core/uart/README.md
+++ b/hw/application_fpga/core/uart/README.md
@@ -24,6 +24,11 @@ in order to hit the center of the bits. For example, a clock of 18 MHz
 and a target bit rate of 62500 bps yields:
 Divisor = 18E6 / 62500 = 288
 
+The UART core includes hardware flow control in the form of two CTS
+lines. One input that the core will check before sending bytes, and
+one output to signal to a connected device that the internal FIFO is
+full. The CTS are active-low.
+
 ## API
 
 ```
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
index c37f5c9..a91db36 100644
--- a/hw/application_fpga/core/uart/rtl/uart.v
+++ b/hw/application_fpga/core/uart/rtl/uart.v
@@ -227,7 +227,7 @@ module uart (
           end
 
           ADDR_TX_STATUS: begin
-            tmp_read_data = {31'h0, core_txd_ready & ch552_cts_reg[1]};
+            tmp_read_data = {31'h0, core_txd_ready & !ch552_cts_reg[1]};
           end
 
           default: begin
diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v
index 0963796..a185b76 100644
--- a/hw/application_fpga/core/uart/rtl/uart_fifo.v
+++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v
@@ -105,7 +105,7 @@ module uart_fifo (
       out_ptr_reg  <= 9'h0;
       byte_ctr_reg <= 9'h0;
       in_ack_reg   <= 1'h0;
-      fpga_cts_reg <= 1'h1;
+      fpga_cts_reg <= 1'h0;
     end
     else begin
       in_ack_reg <= in_ack_new;
@@ -127,10 +127,10 @@ module uart_fifo (
       end
 
       if (byte_ctr_reg >= 9'd486) begin  // FIFO is filled to ~95% or more
-        fpga_cts_reg <= 0;  // Signal to not send more data
+        fpga_cts_reg <= 1;  // Signal to not send more data
       end
       else begin
-        fpga_cts_reg <= 1;  // Signal to send more data
+        fpga_cts_reg <= 0;  // Signal to send more data
       end
 
     end