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Doc: move implementation details of RAM scrambling to RAM core

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Daniel Jobson 2024-11-20 15:36:27 +01:00
parent de8fcb8768
commit 1941a22007
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16
hw/application_fpga/core/ram/README.md
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@ -23,6 +23,22 @@ ram_data_rand inputs as seeds for the scrambling mechanism. When data
is read out it is descrambled before sent out on the read_data output
port. The scrambling functionality does not add latency.
The memory protection is based on two separate mechanisms:
1. Address randomisation
2. Address dependent data randomization
The address randomization is implemented by XORing the RAM address
with the contents of the ADDR\_RAM\_ADDR\_RAND register in the tk1
core. The result is used as the RAM address.
The data randomization is implemented by XORing the data written to
the RAM with the contents of the ADDR\_RAM\_DATA\_RAND register in the
tk1 core as well as XORing with the CPU address. This means that the
same data written to two different addresses will be scrambled
differently. The same pair or XOR operations is also performed on the
data read out from the RAM.
Note: the scrambling mechanism is NOT a cryptographically secure
function. Even if it was, a 32 bit key would be too short to add any
security.