Update PicoRV32 clock frequency to 24 MHz

Include a seed value for nextpnr to get a layout that
reaches 24 MHz.
This commit is contained in:
Jonas Thörnblad 2024-10-22 15:27:53 +02:00
parent c6e8b6930c
commit 1651a1a666
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GPG key ID: 2D318AD00A326F95
5 changed files with 13 additions and 12 deletions

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@ -76,13 +76,13 @@ module clk_reset_gen #(
//
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
//
// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
// Given the 12 MHz HFOSC clock set above, we get a final 24 MHz:
//
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
// (12000000 * (63 + 1)) / (2^5 * (0 + 1)) = 24000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVF(7'd63), // DIVF = 63
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (

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@ -81,9 +81,9 @@ the implementation:
- 16 oscillators in each group
- 64 bits collected before setting the ready flag
With the TKey device running at 18 MHz this means that we sample bits
at 4.3 kbps. Since we sample twice to produce a single bit, the
effective raw bitrate is 2.1 kbps.
With the TKey device running at 24 MHz this means that we sample bits
at 5.8 kbps. Since we sample twice to produce a single bit, the
effective raw bitrate is 2.9 kbps.
The 64 bits collected means that there is a separation of at least 32
collected entropy bits between bits in the words read out.

View file

@ -83,10 +83,10 @@ module uart (
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 21 MHz, 62500 bps
// Divisor = 21E6 / 62500 = 336
// Clock: 24 MHz, 62500 bps
// Divisor = 24E6 / 62500 = 384
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd336;
localparam DEFAULT_BIT_RATE = 16'd384;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;