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PoC: tb: Update tk1 test bench with new ports

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Fixing tests that broke when adding interrupt based syscalls
This commit is contained in:
Mikael Ågren 2024-12-18 08:57:49 +01:00
parent 43239759e6
commit 1179324f10
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GPG Key ID: E02DA3D397792C46
1 changed files with 13 additions and 3 deletions
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16
hw/application_fpga/core/tk1/tb/tb_tk1.v
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@ -76,7 +76,7 @@ module tb_tk1 ();
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_cpu_trap; reg tb_cpu_trap;
wire tb_system_mode; wire tb_rw_locked;
reg [31 : 0] tb_cpu_addr; reg [31 : 0] tb_cpu_addr;
reg tb_cpu_instr; reg tb_cpu_instr;
@ -95,6 +95,10 @@ module tb_tk1 ();
wire tb_gpio3; wire tb_gpio3;
wire tb_gpio4; wire tb_gpio4;
reg tb_access_level_hi;
wire tb_fw_ram_en;
wire tb_spi_ss; wire tb_spi_ss;
wire tb_spi_sck; wire tb_spi_sck;
wire tb_spi_mosi; wire tb_spi_mosi;
@ -122,7 +126,7 @@ module tb_tk1 ();
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.cpu_trap(tb_cpu_trap), .cpu_trap(tb_cpu_trap),
.system_mode(tb_system_mode), .rw_locked(tb_rw_locked),
.cpu_addr (tb_cpu_addr), .cpu_addr (tb_cpu_addr),
.cpu_instr (tb_cpu_instr), .cpu_instr (tb_cpu_instr),
@ -141,6 +145,10 @@ module tb_tk1 ();
.gpio3(tb_gpio3), .gpio3(tb_gpio3),
.gpio4(tb_gpio4), .gpio4(tb_gpio4),
.access_level_hi(tb_access_level_hi),
.fw_ram_en(tb_fw_ram_en),
.spi_ss (tb_spi_ss), .spi_ss (tb_spi_ss),
.spi_sck (tb_spi_sck), .spi_sck (tb_spi_sck),
.spi_mosi(tb_spi_mosi), .spi_mosi(tb_spi_mosi),
@ -192,7 +200,7 @@ module tb_tk1 ();
$display("------------"); $display("------------");
if (tb_main_monitor) begin if (tb_main_monitor) begin
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("tb_cpu_trap: 0x%1x, system_mode: 0x%1x", tb_cpu_trap, tb_system_mode); $display("tb_cpu_trap: 0x%1x, system_mode: 0x%1x", tb_cpu_trap, dut.system_mode);
$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x", $display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap); tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand, $display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand,
@ -277,6 +285,8 @@ module tb_tk1 ();
tb_gpio1 = 1'h0; tb_gpio1 = 1'h0;
tb_gpio2 = 1'h0; tb_gpio2 = 1'h0;
tb_access_level_hi = 1'h0;
tb_cs = 1'h0; tb_cs = 1'h0;
tb_we = 1'h0; tb_we = 1'h0;
tb_address = 8'h0; tb_address = 8'h0;