mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-07-23 07:01:03 -04:00
ch552: Use the new hardware CTS signals for UART access
- Use CTS signals to let the FPGA and CH552 signal each other that it is OK send UART data. - Update the CH552 rx and frame handling logic. - Fix minor spelling errors and indentation
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ab4ef5fdf9
commit
0a634c76da
4 changed files with 237 additions and 93 deletions
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@ -137,7 +137,8 @@ void putchar(char c)
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SBUF = c;
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}
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char getchar() {
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char getchar(void)
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{
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while(!RI); /* assumes UART is initialized */
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RI = 0;
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return SBUF;
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@ -152,7 +153,8 @@ int putchar(int c)
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return c;
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}
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int getchar() {
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int getchar(void)
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{
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while(!RI); /* assumes UART is initialized */
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RI = 0;
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return SBUF;
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@ -198,3 +200,68 @@ void gpio_unset(uint8_t pin)
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break;
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}
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}
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uint8_t gpio_get(uint8_t pin)
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{
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uint8_t ret = 0;
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switch (pin) {
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case 0x10: // p1.4
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ret = P1 & 0x10;
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break;
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case 0x20: // p1.5
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ret = P1 & 0x20;
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break;
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default: // do nothing, unsupported pin.
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ret = 0xff;
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break;
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}
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return ret;
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}
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// Set pin p1.4 to GPIO input mode. (FPGA_CTS)
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void gpio_init_p1_4_in()
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{
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// p1.4
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P1_MOD_OC &= ~0x10; // Output Mode: 0 = Push-pull output, 1 = Open-drain output
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P1_DIR_PU &= ~0x10; // Port Direction Control and Pull-up Enable Register:
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// Push-pull output mode:
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// 0 = Input.
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// 1 = Output
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// Open-drain output mode:
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// 0 = Pull-up resistor disabled
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// 1 = Pull-up resistor enabled
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}
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// Read status of pin 1.4
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uint8_t gpio_p1_4_get(void)
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{
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return (P1 & 0x10); // p1.4
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}
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// Set pin p1.5 to GPIO output mode. (CH552_CTS)
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void gpio_init_p1_5_out()
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{
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// p1.5
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P1_MOD_OC &= ~0x20; // Output Mode: 0 = Push-pull output, 1 = Open-drain output
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P1_DIR_PU |= 0x20; // Port Direction Control and Pull-up Enable Register:
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// Push-pull output mode:
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// 0 = Input.
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// 1 = Output
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// Open-drain output mode:
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// 0 = Pull-up resistor disabled
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// 1 = Pull-up resistor enabled
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}
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// Set p1.5 high
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void gpio_p1_5_set(void)
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{
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P1 |= 0x20; // p1.4
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}
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// Set p1.5 low
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void gpio_p1_5_unset(void)
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{
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P1 &= ~0x20;
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}
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