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FPGA: Fix linting of tk1 core

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Add simultion models of udi_rom and sb_rbga_drv
      to lint-top target.

      Add ignore statements in tb_sb_rgba_drv to silence
      Verilator on parameters and signals not used in
      the sim model.

      Use RGBLEDEN in simulation model

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-07 11:13:19 +02:00 committed by dehanj
parent cadf8e9849
commit 09df7ae97f
No known key found for this signature in database
GPG Key ID: 3707A9DBF4BB8F1A
2 changed files with 21 additions and 14 deletions
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20
hw/application_fpga/core/tk1/tb/sb_rgba_drv.v
View File

@ -16,24 +16,30 @@
`default_nettype none
module SB_RGBA_DRV (
output wire RGB0,
output wire RGB1,
output wire RGB2,
input wire RGBLEDEN,
input wire RGB0PWM,
input wire RGB1PWM,
input wire RGB2PWM,
input wire CURREN
/* verilator lint_off UNUSEDSIGNAL */
input wire CURREN,
/* verilator lint_on UNUSEDSIGNAL */
output wire RGB0,
output wire RGB1,
output wire RGB2
);
/* verilator lint_off UNUSEDPARAM */
parameter CURRENT_MODE = 1;
parameter RGB0_CURRENT = 8'h0;
parameter RGB1_CURRENT = 8'h0;
parameter RGB2_CURRENT = 8'h0;
/* verilator lint_on UNUSEDPARAM */
assign RGB0 = RGB0PWM;
assign RGB1 = RGB1PWM;
assign RGB2 = RGB2PWM;
assign RGB0 = RGB0PWM & RGBLEDEN;
assign RGB1 = RGB1PWM & RGBLEDEN;
assign RGB2 = RGB2PWM & RGBLEDEN;
endmodule // SB_RGBA_DRV

5
hw/application_fpga/core/tk1/toolruns/Makefile
View File

@ -13,6 +13,7 @@
TOP_SRC=../rtl/tk1.v
TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
LINT_SRC=../rtl/tk1.v ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
CC = iverilog
CC_FLAGS = -Wall
@ -32,8 +33,8 @@ sim-top: top.sim
./top.sim
lint-top: $(TOP_SRC)
$(LINT) $(LINT_FLAGS) $(TOP_SRC)
lint-top: $(LINT_SRC)
$(LINT) $(LINT_FLAGS) $(LINT_SRC)
clean: