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fpga/testfw: Update clock frequency to 24 MHz

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Reconfigure the baudrate to keep 500 kbaud.

Correct a forgotten test in testfw that wasn't updated the last time
frequency was raised in commit
75b028505f in June 17, 2024.
This commit is contained in:
Jonas Thörnblad 2025-01-09 15:15:16 +01:00 • committed by Mikael Ågren
parent 0a634c76da
commit 07dc20e4e1
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GPG key ID: E02DA3D397792C46
4 changed files with 10 additions and 9 deletions
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6
hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
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@ -76,13 +76,13 @@ module clk_reset_gen #(
//
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
//
// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
// Given the 12 MHz HFOSC clock set above, we get a final 24 MHz:
//
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
// (12000000 * (63 + 1)) / (2^5 * (0 + 1)) = 24000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVF(7'd63), // DIVF = 63
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (

6
hw/application_fpga/core/uart/rtl/uart.v
View file

@ -82,10 +82,10 @@ module uart (
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 21 MHz, 500 kbps
// Divisor = 21E6 / 500E3 = 42
// Clock: 24 MHz, 500 kbps
// Divisor = 24E6 / 500E3 = 48
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd42;
localparam DEFAULT_BIT_RATE = 16'd48;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;