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Add testbench targets on top-level
The testbenches live in their own Makefiles under hw/application_fpga/core/*/toolruns (except picorv32). Let's add a top-level target to build and run them. In order to run core testbenches, use cd hw/application_fpga make tb or if using Podman: cd contrib make run-tb to run the same target in a container.
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2 changed files with 25 additions and 1 deletions
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@ -6,9 +6,13 @@
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# HW targets as well as its firmware.
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#
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#
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# Copyright (C) 2022, 2023 - Tillitis AB
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# Copyright (C) 2022-2024 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#
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# Please note: When creating a new cores and adding more testbenches,
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# please update the tb target below to include it as well.
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#
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#=======================================================================
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#-------------------------------------------------------------------
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@ -207,6 +211,18 @@ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
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make -C verilated -f Vapplication_fpga.mk
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.PHONY: verilator
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#-------------------------------------------------------------------
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# Run all testbenches
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#-------------------------------------------------------------------
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tb:
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make -C core/timer/toolruns sim-top
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make -C core/tk1/toolruns sim-top
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make -C core/touch_sense/toolruns sim-top
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make -C core/trng/toolruns sim-top
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make -C core/uart/toolruns sim-top
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make -C core/uds/toolruns sim-top
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.PHONY: tb
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#-------------------------------------------------------------------
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# Main FPGA build flow.
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@ -333,6 +349,7 @@ help:
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@echo "bram_fw.hex Build a fake BRAM file that will be filled in later after place-n-route."
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@echo "verilator Build Verilator simulation program"
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@echo "lint Run lint on Verilog source files."
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@echo "tb Run all testbenches"
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@echo "prog_flash Program device flash with FGPA bitstream including firmware (using the RPi Pico-based programmer)."
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@echo "prog_flash_testfw Program device flash as above, but with testfw."
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@echo "clean Delete all generated files."
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