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Change to a single run bit and update access control

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This commit is contained in:
Joachim Strömbergson 2022-10-13 14:58:39 +02:00
parent 5e5550461f
commit 00d180d34e
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
3 changed files with 33 additions and 34 deletions
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47
hw/application_fpga/core/timer/rtl/timer.v
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@ -30,12 +30,11 @@ module timer(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_CTRL = 8'h08; localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0; localparam CTRL_RUN_BIT = 0;
localparam CTRL_STOP_BIT = 1;
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0; localparam STATUS_READY_BIT = 0;
localparam ADDR_PRESCALER = 8'h0a; localparam ADDR_PRESCALER = 8'h0a;
localparam ADDR_TIMER = 8'h0b; localparam ADDR_TIMER = 8'h0b;
@ -50,11 +49,8 @@ module timer(
reg [31 : 0] timer_reg; reg [31 : 0] timer_reg;
reg timer_we; reg timer_we;
reg start_reg; reg run_reg;
reg start_new; reg run_we;
reg stop_reg;
reg stop_new;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -80,10 +76,9 @@ module timer(
timer_core core( timer_core core(
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.prescaler_value(prescaler_reg), .prescaler_init(prescaler_reg),
.timer_value(timer_reg), .timer_init(timer_reg),
.start(start_reg), .run(run_reg),
.stop(stop_reg),
.curr_timer(core_curr_timer), .curr_timer(core_curr_timer),
.ready(core_ready) .ready(core_ready)
); );
@ -95,15 +90,15 @@ module timer(
always @ (posedge clk) always @ (posedge clk)
begin : reg_update begin : reg_update
if (!reset_n) begin if (!reset_n) begin
start_reg <= 1'h0; run_reg <= 1'h0;
stop_reg <= 1'h0;
prescaler_reg <= 32'h0; prescaler_reg <= 32'h0;
timer_reg <= 32'h0; timer_reg <= 32'h0;
end end
else begin else begin
start_reg <= start_new; if (run_we) begin
stop_reg <= stop_new; run_reg <= write_data[CTRL_RUN_BIT];
end
if (prescaler_we) begin if (prescaler_we) begin
prescaler_reg <= write_data; prescaler_reg <= write_data;
@ -123,8 +118,7 @@ module timer(
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @*
begin : api begin : api
start_new = 1'h0; run_we = 1'h0;
stop_new = 1'h0;
prescaler_we = 1'h0; prescaler_we = 1'h0;
timer_we = 1'h0; timer_we = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;
@ -135,8 +129,7 @@ module timer(
if (we) begin if (we) begin
if (address == ADDR_CTRL) begin if (address == ADDR_CTRL) begin
start_new = write_data[CTRL_START_BIT]; run_we = 1'h1;
stop_new = write_data[CTRL_STOP_BIT];
end end
if (core_ready) begin if (core_ready) begin
@ -151,6 +144,10 @@ module timer(
end end
else begin else begin
if (address == ADDR_CTRL) begin
tmp_read_data = {31'h0, run_reg};
end
if (address == ADDR_STATUS) begin if (address == ADDR_STATUS) begin
tmp_read_data = {31'h0, core_ready}; tmp_read_data = {31'h0, core_ready};
end end
@ -160,7 +157,11 @@ module timer(
end end
if (address == ADDR_TIMER) begin if (address == ADDR_TIMER) begin
tmp_read_data = core_curr_timer; if (core_ready) begin
tmp_read_data = timer_reg;
end else begin
tmp_read_data = core_curr_timer;
end
end end
end end
end end

17
hw/application_fpga/core/timer/rtl/timer_core.v
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@ -17,10 +17,9 @@ module timer_core(
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire [31 : 0] prescaler_value, input wire [31 : 0] prescaler_init,
input wire [31 : 0] timer_value, input wire [31 : 0] timer_init,
input wire start, input wire run,
input wire stop,
output wire [31 : 0] curr_timer, output wire [31 : 0] curr_timer,
@ -109,7 +108,7 @@ module timer_core(
prescaler_we = 1'h0; prescaler_we = 1'h0;
if (prescaler_set) begin if (prescaler_set) begin
prescaler_new = prescaler_value; prescaler_new = prescaler_init;
prescaler_we = 1'h1; prescaler_we = 1'h1;
end end
else if (prescaler_dec) begin else if (prescaler_dec) begin
@ -128,7 +127,7 @@ module timer_core(
timer_we = 1'h0; timer_we = 1'h0;
if (timer_set) begin if (timer_set) begin
timer_new = timer_value; timer_new = timer_init;
timer_we = 1'h1; timer_we = 1'h1;
end end
else if (timer_dec) begin else if (timer_dec) begin
@ -154,7 +153,7 @@ module timer_core(
case (core_ctrl_reg) case (core_ctrl_reg)
CTRL_IDLE: begin CTRL_IDLE: begin
if (start) if (run)
begin begin
ready_new = 1'h0; ready_new = 1'h0;
ready_we = 1'h1; ready_we = 1'h1;
@ -167,7 +166,7 @@ module timer_core(
CTRL_PRESCALER: begin CTRL_PRESCALER: begin
if (stop) begin if (!run) begin
ready_new = 1'h1; ready_new = 1'h1;
ready_we = 1'h1; ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE; core_ctrl_new = CTRL_IDLE;
@ -188,7 +187,7 @@ module timer_core(
CTRL_TIMER: begin CTRL_TIMER: begin
if (stop) begin if (!run) begin
ready_new = 1'h1; ready_new = 1'h1;
ready_we = 1'h1; ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE; core_ctrl_new = CTRL_IDLE;

3
hw/application_fpga/fw/mta1_mkdf_mem.h
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@ -43,8 +43,7 @@ enum {
MTA1_MKDF_MMIO_TRNG_ENTROPY = MTA1_MKDF_MMIO_TRNG_BASE | 0x80, MTA1_MKDF_MMIO_TRNG_ENTROPY = MTA1_MKDF_MMIO_TRNG_BASE | 0x80,
MTA1_MKDF_MMIO_TIMER_CTRL = MTA1_MKDF_MMIO_TIMER_BASE | 0x20, MTA1_MKDF_MMIO_TIMER_CTRL = MTA1_MKDF_MMIO_TIMER_BASE | 0x20,
MTA1_MKDF_MMIO_TIMER_CTRL_START_BIT = 0, MTA1_MKDF_MMIO_TIMER_CTRL_RUN_BIT = 0,
MTA1_MKDF_MMIO_TIMER_CTRL_STOP_BIT = 1,
MTA1_MKDF_MMIO_TIMER_STATUS = MTA1_MKDF_MMIO_TIMER_BASE | 0x24, MTA1_MKDF_MMIO_TIMER_STATUS = MTA1_MKDF_MMIO_TIMER_BASE | 0x24,
MTA1_MKDF_MMIO_TIMER_STATUS_READY_BIT = 0, MTA1_MKDF_MMIO_TIMER_STATUS_READY_BIT = 0,
MTA1_MKDF_MMIO_TIMER_PRESCALER = MTA1_MKDF_MMIO_TIMER_BASE | 0x28, MTA1_MKDF_MMIO_TIMER_PRESCALER = MTA1_MKDF_MMIO_TIMER_BASE | 0x28,