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FPGA: Add system reset API

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Add API address to trigger system reset.
      When written to will send system_reset signal
      to the reset generator, which then perform a complete
      reset cycle of the FPGA system.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-24 13:27:51 +02:00 • committed by Daniel Jobson
parent b5ba21148d
commit 00599549e3
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GPG key ID: 3707A9DBF4BB8F1A
6 changed files with 69 additions and 4 deletions
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9
hw/application_fpga/rtl/application_fpga.v
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@ -148,6 +148,7 @@ module application_fpga(
wire force_trap;
wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand;
wire tk1_system_reset;
/* verilator lint_on UNOPTFLAT */
@ -155,7 +156,11 @@ module application_fpga(
// Module instantiations.
//----------------------------------------------------------------
clk_reset_gen #(.RESET_CYCLES(200))
reset_gen_inst(.clk(clk), .rst_n(reset_n));
reset_gen_inst(
.sys_reset(tk1_system_reset),
.clk(clk),
.rst_n(reset_n)
);
picorv32 #(
@ -321,6 +326,8 @@ module application_fpga(
.cpu_trap(cpu_trap),
.force_trap(force_trap),
.system_reset(tk1_system_reset),
.ram_addr_rand(ram_addr_rand),
.ram_data_rand(ram_data_rand),