Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-05-02 06:06:24 -04:00
Code Issues Projects Releases Packages Wiki Activity

FPGA: Add system reset API

Browse source 
Add API address to trigger system reset.
      When written to will send system_reset signal
      to the reset generator, which then perform a complete
      reset cycle of the FPGA system.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-24 13:27:51 +02:00 • committed by Daniel Jobson
parent b5ba21148d
commit 00599549e3
No known key found for this signature in database
GPG key ID: 3707A9DBF4BB8F1A
6 changed files with 69 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

9
hw/application_fpga/rtl/application_fpga.v
View file

@ -148,6 +148,7 @@ module application_fpga(
wire force_trap;
wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand;
wire tk1_system_reset;
/* verilator lint_on UNOPTFLAT */
@ -155,7 +156,11 @@ module application_fpga(
// Module instantiations.
//----------------------------------------------------------------
clk_reset_gen #(.RESET_CYCLES(200))
reset_gen_inst(.clk(clk), .rst_n(reset_n));
reset_gen_inst(
.sys_reset(tk1_system_reset),
.clk(clk),
.rst_n(reset_n)
);
picorv32 #(
@ -321,6 +326,8 @@ module application_fpga(
.cpu_trap(cpu_trap),
.force_trap(force_trap),
.system_reset(tk1_system_reset),
.ram_addr_rand(ram_addr_rand),
.ram_data_rand(ram_data_rand),

18
hw/application_fpga/rtl/clk_reset_gen.v
View file

@ -18,6 +18,8 @@
module clk_reset_gen #(parameter RESET_CYCLES = 200)
(
input wire sys_reset,
output wire clk,
output wire rst_n
);
@ -33,6 +35,12 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
reg rst_n_reg = 1'h0;
reg rst_n_new;
reg sys_reset_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire hfosc_clk;
wire pll_clk;
@ -93,7 +101,8 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
rst_n_reg <= rst_n_new;
rst_n_reg <= rst_n_new;
sys_reset_reg <= sys_reset;
if (rst_ctr_we)
rst_ctr_reg <= rst_ctr_new;
@ -109,7 +118,12 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;
if (rst_ctr_reg < RESET_CYCLES) begin
if (sys_reset_reg) begin
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h1;
end
else if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;