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FPGA: Add system reset API

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Add API address to trigger system reset.
      When written to will send system_reset signal
      to the reset generator, which then perform a complete
      reset cycle of the FPGA system.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-24 13:27:51 +02:00 • committed by Daniel Jobson
parent b5ba21148d
commit 00599549e3
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GPG key ID: 3707A9DBF4BB8F1A
6 changed files with 69 additions and 4 deletions
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26
hw/application_fpga/core/tk1/README.md
View file

@ -248,6 +248,32 @@ see the datasheet:
https://www.mouser.se/datasheet/2/949/w25q80dv_dl_revh_10022015-1489677.pdf
## System Reset
The TK1 includes an ability for FW and applications to trigger a
hardware reset of the FPGA by writing to an API address.
The hardware reset will force all registers that are in the Tkey FPGA
design reset circuit to be reset to their default values. Basically
this is all registers in the Tkey FPGA design.
The reset will not clear the RAM. However since the CPU program
counter is reset to its reset vector, the CPU will unconditionally
start executing the FW. As part of the device initialization, the FW
will fill the RAM with random data, overwriting any app and
data present in the RAM before the reset was triggered.
The hardware reset will not force the FPGA to read its
configuration. That requires a power cycle of the Tkey device.
The reset is controlled by the following API address. Note that
any value written to the address will trigger the reset.
```
localparam ADDR_SYSTEM_RESET = 8'h70;
```
## Implementation
The core is implemented as a single module. Future versions will

16
hw/application_fpga/core/tk1/rtl/tk1.v
View file

@ -24,6 +24,7 @@ module tk1(
input wire cpu_instr,
input wire cpu_valid,
output wire force_trap,
output system_reset,
output wire [14 : 0] ram_addr_rand,
output wire [31 : 0] ram_data_rand,
@ -93,6 +94,8 @@ module tk1(
localparam ADDR_CPU_MON_FIRST = 8'h61;
localparam ADDR_CPU_MON_LAST = 8'h62;
localparam ADDR_SYSTEM_RESET = 8'h70;
`ifdef INCLUDE_SPI_MASTER
localparam ADDR_SPI_EN = 8'h80;
localparam ADDR_SPI_XFER = 8'h81;
@ -146,6 +149,9 @@ module tk1(
reg [31 : 0] ram_data_rand_reg;
reg ram_data_rand_we;
reg system_reset_reg;
reg system_reset_new;
reg cpu_mon_en_reg;
reg cpu_mon_en_we;
reg [31 : 0] cpu_mon_first_reg;
@ -196,6 +202,8 @@ module tk1(
assign ram_addr_rand = ram_addr_rand_reg;
assign ram_data_rand = ram_data_rand_reg;
assign system_reset = system_reset_reg;
//----------------------------------------------------------------
// Module instance.
@ -276,11 +284,14 @@ module tk1(
ram_addr_rand_reg <= 15'h0;
ram_data_rand_reg <= 32'h0;
force_trap_reg <= 1'h0;
system_reset_reg <= 1'h0;
end
else begin
cpu_trap_ctr_reg <= cpu_trap_ctr_new;
system_reset_reg <= system_reset_new;
gpio1_reg[0] <= gpio1;
gpio1_reg[1] <= gpio1_reg[0];
@ -429,6 +440,7 @@ module tk1(
cdi_mem_we = 1'h0;
ram_addr_rand_we = 1'h0;
ram_data_rand_we = 1'h0;
system_reset_new = 1'h0;
cpu_mon_en_we = 1'h0;
cpu_mon_first_we = 1'h0;
cpu_mon_last_we = 1'h0;
@ -473,6 +485,10 @@ module tk1(
end
end
if (address == ADDR_SYSTEM_RESET) begin
system_reset_new = 1'h1;
end
if (address == ADDR_BLAKE2S) begin
if (!switch_app_reg) begin
blake2s_addr_we = 1'h1;