Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity
508 Commits 33 Branches 14 Tags 31 MiB

Default Branch

main

81950ef7b2 · fw: remove warning of missing prototypes when building with QEMU console · Updated 2024-09-19 10:52:04 -04:00
 ZIP  TAR.GZ

Branches

spi_clk_two_cycles

6045aacadc · FPGA: Remove the NEXT state in SPI master FSM · Updated 2024-06-18 09:11:56 -04:00
26
4
 ZIP  TAR.GZ
spi_clk_three_cycles

0e9df05ad0 · FPGA: Experimental increase in SPI clock frequency · Updated 2024-06-18 07:14:28 -04:00
26
3
 ZIP  TAR.GZ
new_targets

2b213d51b8 · Add a make target and script that runs the secret generation. · Updated 2024-06-14 07:52:47 -04:00
32
1
 ZIP  TAR.GZ
addr_in_name_fail

c9a2dbe18d · Change name of register to contain 'addr' changes the FPGA bitstream · Updated 2024-06-04 07:29:10 -04:00
39
1
 ZIP  TAR.GZ
add_finger_present

c96363aec0 · Add finger present API and bit. Update README · Updated 2024-05-20 04:57:00 -04:00
39
1
 ZIP  TAR.GZ
fix_lint_uds_core

5a396d7f51 · Add model for SB_LUT4 to allow linting · Updated 2024-04-25 08:12:48 -04:00
39
1
 ZIP  TAR.GZ
199-add-support-for-host-based-device-reset

bd45d3b0dd · Move reset control and status into the tk1 core · Updated 2024-04-22 10:14:10 -04:00
41
3
 ZIP  TAR.GZ
186_disable_cdi_access

d620ab1a03 · Write to CDI in app mode blocks read access · Updated 2024-04-22 10:13:12 -04:00
41
2
 ZIP  TAR.GZ
186_disable_cdi_access_orig

a17a413e81 · Write to CDI in app mode blocks read access · Updated 2024-04-16 04:29:21 -04:00
44
2
 ZIP  TAR.GZ
uwg30

bec34f0b11 · Build FPGA for the uwg30 wcsp package · Updated 2024-03-14 09:41:18 -04:00
83
1
 ZIP  TAR.GZ
uart_tx_debug_pin

71d091fcd5 · Add tx debug port functionality with API controlled select · Updated 2024-02-05 13:12:51 -05:00
84
1
 ZIP  TAR.GZ
blake2s

6e6c2ab3ca · Add blake2s core · Updated 2023-09-08 08:52:40 -04:00
96
1
 ZIP  TAR.GZ