2022-09-19 02:51:11 -04:00
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//======================================================================
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//
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// figaro.v
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// --------
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// Top level wrapper for the figaro core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module figaro(
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input wire clk,
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input wire reset_n,
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input wire cs,
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input wire we,
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input wire [7 : 0] address,
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2022-10-06 07:23:30 -04:00
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/* verilator lint_off UNUSED */
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2022-09-19 02:51:11 -04:00
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input wire [31 : 0] write_data,
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2022-10-06 07:23:30 -04:00
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/* verilator lint_on UNUSED */
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2022-09-19 02:51:11 -04:00
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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2022-10-11 02:45:06 -04:00
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// API
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2022-09-19 02:51:11 -04:00
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localparam ADDR_STATUS = 8'h09;
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localparam STATUS_READY_BIT = 0;
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localparam ADDR_ENTROPY = 8'h20;
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2022-10-11 02:45:06 -04:00
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// Total number of ROSCs will be 2 x NUM_ROSC.
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localparam SAMPLE_RATE = 16'h1000;
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localparam NUM_ROSC = 16;
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2022-10-11 02:45:06 -04:00
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localparam CTRL_SAMPLE1 = 0;
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localparam CTRL_SAMPLE2 = 1;
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localparam CTRL_DATA_READY = 2;
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//----------------------------------------------------------------
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2022-10-11 02:45:06 -04:00
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// Registers with associated wires.
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//----------------------------------------------------------------
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reg [16 : 0] cycle_ctr_reg;
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reg [16 : 0] cycle_ctr_new;
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reg cycle_ctr_done;
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reg cycle_ctr_rst;
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reg [4 : 0] bit_ctr_reg;
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reg [4 : 0] bit_ctr_new;
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reg bit_ctr_we;
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2022-10-11 02:45:06 -04:00
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reg [31 : 0] entropy_reg;
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reg [31 : 0] entropy_new;
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reg entropy_we;
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reg [1 : 0] sample1_reg;
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reg [1 : 0] sample1_new;
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reg sample1_we;
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reg [1 : 0] sample2_reg;
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reg [1 : 0] sample2_new;
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reg sample2_we;
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reg data_ready_reg;
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reg data_ready_new;
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reg data_ready_we;
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reg data_ready_set;
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reg data_ready_rst;
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reg [1 : 0] rosc_ctrl_reg;
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reg [1 : 0] rosc_ctrl_new;
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reg rosc_ctrl_we;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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reg [31 : 0] tmp_read_data;
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reg tmp_ready;
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/* verilator lint_off UNOPTFLAT */
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wire [(NUM_ROSC - 1) : 0] f;
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/* verilator lint_on UNOPTFLAT */
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/* verilator lint_off UNOPTFLAT */
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wire [(NUM_ROSC - 1) : 0] g;
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2022-10-08 12:37:48 -04:00
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/* verilator lint_on UNOPTFLAT */
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2022-09-19 02:51:11 -04:00
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = tmp_ready;
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//----------------------------------------------------------------
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// oscillators.
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//
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// 32 single inverters, each connect to itself.
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//----------------------------------------------------------------
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genvar i;
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generate
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for(i = 0 ; i < NUM_ROSC ; i = i + 1)
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begin: oscillators
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/* verilator lint_off PINMISSING */
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_f (.I0(f[i]), .O(f[i]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_g (.I0(g[i]), .O(g[i]));
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/* verilator lint_off PINMISSING */
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end
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endgenerate
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//---------------------------------------------------------------
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// reg_update
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//---------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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cycle_ctr_reg <= 16'h0;
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bit_ctr_reg <= 5'h0;
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sample1_reg <= 2'h0;
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sample2_reg <= 2'h0;
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entropy_reg <= 32'h0;
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data_ready_reg <= 1'h0;
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rosc_ctrl_reg <= CTRL_SAMPLE1;
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end
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else begin
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cycle_ctr_reg <= cycle_ctr_new;
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if (bit_ctr_we) begin
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bit_ctr_reg <= bit_ctr_new;
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end
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2022-10-11 02:45:06 -04:00
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if (sample1_we) begin
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sample1_reg <= sample1_new;
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end
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if (sample2_we) begin
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sample2_reg <= sample2_new;
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end
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if (entropy_we) begin
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entropy_reg <= entropy_new;
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end
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2022-10-11 02:45:06 -04:00
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if (data_ready_we) begin
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data_ready_reg <= data_ready_new;
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end
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if (rosc_ctrl_we) begin
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rosc_ctrl_reg <= rosc_ctrl_new;
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end
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end
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end
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//----------------------------------------------------------------
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// api
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//
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// The interface command decoding logic.
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//----------------------------------------------------------------
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always @*
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begin : api
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data_ready_rst = 1'h0;
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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if (cs) begin
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tmp_ready = 1'h1;
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if (!we) begin
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if (address == ADDR_STATUS) begin
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tmp_read_data = {31'h0, data_ready_reg};
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end
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if (address == ADDR_ENTROPY) begin
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tmp_read_data = entropy_reg;
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data_ready_rst = 1'h1;
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end
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end
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end
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end // api
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//----------------------------------------------------------------
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// data_ready_logic
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//----------------------------------------------------------------
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always @*
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begin : data_ready_logic
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data_ready_new = 1'h0;
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data_ready_we = 1'h0;
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if (data_ready_set) begin
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data_ready_new = 1'h1;
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data_ready_we = 1'h1;
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end else if (data_ready_rst) begin
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data_ready_new = 1'h0;
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data_ready_we = 1'h1;
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end
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end
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//----------------------------------------------------------------
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// cycle_ctr_logic
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//----------------------------------------------------------------
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always @*
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begin : cycle_ctr_logic
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cycle_ctr_done = 1'h0;
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cycle_ctr_new = cycle_ctr_reg + 1'h1;
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if (cycle_ctr_rst) begin
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cycle_ctr_new = 24'h0;
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end
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if (cycle_ctr_reg == SAMPLE_RATE) begin
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cycle_ctr_done = 1'h1;
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end
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end
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2022-10-08 12:37:48 -04:00
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//----------------------------------------------------------------
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// rosc_ctrl_logic
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//----------------------------------------------------------------
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always @*
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begin : rosc_ctrl_logic
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reg xor_f;
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reg xor_g;
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reg xor_sample1;
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reg xor_sample2;
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sample1_we = 1'h0;
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sample2_we = 1'h0;
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cycle_ctr_rst = 1'h0;
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data_ready_set = 1'h0;
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entropy_we = 1'h0;
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bit_ctr_new = 6'h0;
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bit_ctr_we = 1'h0;
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rosc_ctrl_new = CTRL_SAMPLE1;
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rosc_ctrl_we = 1'h0;
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xor_f = ^f;
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xor_g = ^g;
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xor_sample1 = ^sample1_reg;
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xor_sample2 = ^sample2_reg;
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sample1_new = {sample1_reg[0], xor_f};
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sample2_new = {sample2_reg[0], xor_g};
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entropy_new = {entropy_reg[30 : 0], xor_sample2};
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if (bit_ctr_reg == 31) begin
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data_ready_set = 1'h1;
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end
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case (rosc_ctrl_reg)
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CTRL_SAMPLE1: begin
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if (cycle_ctr_done) begin
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cycle_ctr_rst = 1'h1;
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sample1_we = 1'h1;
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sample2_we = 1'h1;
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rosc_ctrl_new = CTRL_SAMPLE2;
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rosc_ctrl_we = 1'h1;
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end
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end
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CTRL_SAMPLE2: begin
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if (cycle_ctr_done) begin
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cycle_ctr_rst = 1'h1;
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sample1_we = 1'h1;
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sample2_we = 1'h1;
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rosc_ctrl_new = CTRL_DATA_READY;
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rosc_ctrl_we = 1'h1;
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end
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end
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CTRL_DATA_READY: begin
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if (xor_sample1 ^ xor_sample2) begin
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entropy_we = 1'h1;
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bit_ctr_new = bit_ctr_reg + 1'h1;
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bit_ctr_we = 1'h1;
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end
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rosc_ctrl_new = CTRL_SAMPLE1;
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rosc_ctrl_we = 1'h1;
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end
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default: begin
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end
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endcase // case (rosc_ctrl_reg)
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end
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2022-09-19 02:51:11 -04:00
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endmodule // figaro
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//======================================================================
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// EOF figaro.v
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//======================================================================
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