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30 lines
859 B
Markdown
30 lines
859 B
Markdown
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# trng
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Implementation of the FiGaRO TRNG for FPGAs
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## Introduction
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# figaro
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## Status
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First version completed. In testing. Use with caution.
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## Introduction
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This is a an implementation of the FiGaRO true random
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number generator (TRNG) [1]. The main FPGA target is Lattice iCE40
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UltraPlus, but adaption to other FPGAs should be easy to do.
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## Implementation details
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The implementation instantiates four FiRO and four GaRO modules. The
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modules includes state sampling. The polynomials used for the
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oscillators are given by equotions (9)..(16) in paper [1]. The eight
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outputs are then XORed together to form a one bit random value.
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The random bit value is sampled at a rate controlled by a 24 bit
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divisor.
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## References
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[1] [True Random Number Generator Based on Fibonacci-Galois
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Ring Oscillators for FPGA](https://www.mdpi.com/2076-3417/11/8/3330/pdf)
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