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https://github.com/tillitis/tillitis-key1.git
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76 lines
1.7 KiB
Makefile
76 lines
1.7 KiB
Makefile
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#===================================================================
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#
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# Makefile
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# --------
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# Makefile for building the timer core and top simulations.
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#
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#
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# Author: Joachim Strombergson
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# Copyright (C) 2022 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#===================================================================
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CORE_SRC=../rtl/timer_core.v
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TB_CORE_SRC =../tb/tb_timer_core.v
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TOP_SRC=../rtl/timer.v $(CORE_SRC)
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TB_TOP_SRC =../tb/tb_timer.v
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CC = iverilog
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CC_FLAGS = -Wall
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LINT = verilator
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LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
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all: top.sim core.sim
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top.sim: $(TB_TOP_SRC) $(TOP_SRC)
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$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC)
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core.sim: $(TB_CORE_SRC) $(CORE_SRC)
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$(CC) $(CC_FLAGS) -o core.sim $(TB_CORE_SRC) $(CORE_SRC)
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sim-top: top.sim
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./top.sim
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sim-core: core.sim
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./core.sim
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lint-core: $(CORE_SRC)
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$(LINT) $(LINT_FLAGS) $(CORE_SRC)
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lint-top: $(TOP_SRC)
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$(LINT) $(LINT_FLAGS) $(TOP_SRC)
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clean:
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rm -f top.sim
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rm -f core.sim
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help:
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@echo "Build system for simulation of Prince core"
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@echo ""
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@echo "Supported targets:"
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@echo "------------------"
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@echo "all: Build all simulation targets."
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@echo "top.sim: Build top level simulation target."
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@echo "core.sim: Build core level simulation target."
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@echo "sim-top: Run top level simulation."
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@echo "sim-core: Run core level simulation."
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@echo "lint-core: Lint core rtl source files."
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@echo "lint-core: Lint top rtl source files."
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@echo "clean: Delete all built files."
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#===================================================================
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# EOF Makefile
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#===================================================================
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